公开(公告)号：US20190259695A1

公开(公告)日：2019-08-22

申请号：US15902949

申请日：2018-02-22

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Vadim Heyfitch

IPC: H01L23/498 ,  G01R31/317 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/64 ,  H01L21/48 ,  H01L21/56

Abstract: A chip package and method of fabricating the same are described herein. The chip package includes a high speed data transmission line that has an inter-die region through which a signal transmission line couples a first die to a second die. The signal transmission line has a resistance greater than an equivalent base resistance (EBR) of a copper line, which reduces oscillation within the transmission line.

公开(公告)号：US11282776B2

公开(公告)日：2022-03-22

申请号：US15902949

申请日：2018-02-22

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Vadim Heyfitch

IPC: H01L21/48 ,  H01L23/498 ,  G01R31/317 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/64 ,  H01L21/56

Abstract: A chip package and method of fabricating the same are described herein. The chip package includes a high speed data transmission line that has an inter-die region through which a signal transmission line couples a first die to a second die. The signal transmission line has a resistance greater than an equivalent base resistance (EBR) of a copper line, which reduces oscillation within the transmission line.

公开(公告)号：US11127643B1

公开(公告)日：2021-09-21

申请号：US16588253

申请日：2019-09-30

Applicant: Xilinx, Inc.

Inventor： Vadim Heyfitch ,  Jaspreet Singh Gandhi

IPC: H01L21/66 ,  H01L23/498 ,  H01L23/00

Abstract: A device includes a die with perimeters associated therewith, a substrate, and a test channel. The die is coupled to the substrate via a plurality of C4 bumps on a first side of the substrate. The substrate has connections on a second side of the substrate, opposite to the first side. A first connection connects a C4 bump on the first side of the substrate to a connection on the second side using a metal layer. The test channel is positioned within the substrate and further positioned outside of the perimeter of the die coupled to the substrate. The test channel is positioned at substantially a same depth as the metal layer of the first connection. A probe connecting to the test channel via pads positioned on a same side of the substrate that provides electrical characteristics that is substantially the same as electrical characteristics of the first connection.