公开(公告)号：US09008204B1

公开(公告)日：2015-04-14

申请号：US14267853

申请日：2014-05-01

Applicant: Xilinx, Inc.

Inventor： Christopher H. Dick

IPC: H04L27/28 ,  H04K1/10 ,  H04L27/26

CPC classification number: H04L27/2627 ,  H04L27/263

Abstract: An apparatus relates generally to OFDM. In this apparatus, modulators are coupled to receive data inputs. Each of the modulators includes IDFT blocks coupled to output a first and a second N-point transform, and a 2N-point transform to provide discrete time domain signals for the data inputs. A switch and frequency translation block is coupled to receive the discrete time domain signals. RF ports are coupled to the switch and frequency translation block. The switch and frequency translation block is configured to allocate a combination of outputs from two or more of the IDFT blocks to a same RF port of the RF ports and to translate frequency of at least one of the outputs from the two or more of the IDFT blocks to provide the OFDM of the outputs from the two or more of the IDFT blocks onto the same RF port of the RF ports.

Abstract translation: 一种装置一般涉及OFDM。 在该装置中，调制器被耦合以接收数据输入。 每个调制器包括被耦合以输出第一和第二N点变换的IDFT块，以及2N点变换以提供用于数据输入的离散时域信号。 耦合开关和频率转换模块以接收离散时域信号。 RF端口耦合到开关和频率平移块。 开关和频率转换块被配置为将两个或更多个IDFT块的输出的组合分配给RF端口的相同RF端口，并且将IDFT中的两个或更多个的输出中的至少一个的频率 块，以将来自两个或更多个IDFT块的输出的OFDM提供到RF端口的相同RF端口上。

公开(公告)号：US11586908B1

公开(公告)日：2023-02-21

申请号：US16295405

申请日：2019-03-07

Applicant: Xilinx, Inc.

Inventor： Albert T. Gural ,  Sambhav R. Jain ,  Christopher H. Dick

IPC: G06N3/08 ,  G06K9/62 ,  G06N3/04 ,  G06F40/20

Abstract: Systems and methods for training a neural network model includes providing a quantization function including a quantization log threshold parameter associated with a log value of a quantization threshold. A quantization training to a neural network model is performed to generate quantized neural network parameters. The quantization training includes: generating first values with a first precision for the neural network parameters; performing a first optimization process to generate an updated quantization log threshold parameter; and generating quantized values with a second precision lower than the first precision for the neural network parameters by applying the quantization function with the updated quantization log threshold parameter to the first values. The neural network model with the quantized values for the neural network parameters is provided for performing a task.

公开(公告)号：US11108410B1

公开(公告)日：2021-08-31

申请号：US16112588

申请日：2018-08-24

Applicant: Xilinx, Inc.

Inventor： Richard L. Walke ,  Christopher H. Dick ,  Nihat E. Tunali

IPC: H03M13/11 ,  H03M13/15 ,  H03M13/09

Abstract: A decoder circuit includes a low-density parity-check (LDPC) repository, an LDPC code configurator, and LDPC decoding circuitry. The LDPC repository stores parity-check information associated with one or more LDPC codes. The LDPC code configurator may receive a first LDPC configuration describing a parity-check matrix for a first LDPC code and may update the parity-check information in the LDPC repository to reflect the parity-check matrix for the first LDPC code. The LDPC decoding circuitry may receive a first codeword encoded in accordance with the LDPC code. More specifically, the LDPC decoding circuitry may be configured to read the parity-check information associated with the first LDPC code from the LDPC repository and iteratively decode the first codeword using the parity-check information associated with the first LDPC code.

公开(公告)号：US10673564B1

公开(公告)日：2020-06-02

申请号：US16138414

申请日：2018-09-21

Applicant: Xilinx, Inc.

Inventor： Richard L. Walke ,  Christopher H. Dick ,  William A. Wilkie

IPC: H04L1/00 ,  H03M13/29 ,  H03M13/45 ,  H03M13/11 ,  H04B1/38

Abstract: A modem includes an outer transceiver including a soft decision forward error correction (SD-FEC) circuit, wherein the SD-FEC circuit is hardwired and programmable to perform at least one of encoding or decoding data using a code type selected from a plurality of different code types, and an inner transceiver coupled to the SD-FEC circuit, wherein the inner transceiver is implemented in programmable circuitry.

公开(公告)号：US20200099416A1

公开(公告)日：2020-03-26

申请号：US16142295

申请日：2018-09-26

Applicant: Xilinx, Inc.

Inventor： Christopher H. Dick ,  Hongzhi Zhao ,  Hemang M. Parekh ,  Xiaohan Chen

IPC: H04B3/06 ,  H04B1/04 ,  H04L25/03 ,  H04N7/10

Abstract: A digital predistortion (DPD) system includes an input configured to receive a DPD input signal. In some embodiments, a non-linear datapath is coupled to the input, where the non-linear datapath includes a plurality of parallel datapath elements each coupled to the input. By way of example, each of the plurality of parallel datapath elements is configured to add a different inverse non-linear component to the DPD input signal corresponding to a non-linear component of an amplifier. In various examples, a first combiner combines an output of each of the plurality of datapath elements to generate a first predistortion signal. In some embodiments, the DPD system further includes a linear datapath coupled to the input in parallel with the non-linear datapath to generate a second predistortion signal. In addition, a second combiner combines the first predistortion signal and the second predistortion signal to generate a DPD output signal.

公开(公告)号：US10484012B1

公开(公告)日：2019-11-19

申请号：US15688628

申请日：2017-08-28

Applicant: Xilinx, Inc.

Inventor： Nihat E. Tunali ,  Richard L. Walke ,  Christopher H. Dick

IPC: H03M13/11

Abstract: A decoder circuit includes an input configured to receive an encoded message generated based on a QC-LDPC code. A first layer process unit is configured to process a first layer of a parity check matrix to generate a plurality of log-likelihood ratio (LLR) values corresponding to a plurality of variable nodes associated with the encoded message respectively. The first layer process unit includes a plurality of row process units configured to process a first plurality of rows of the first layer in parallel to generate a plurality of row update values. A layer update unit is configured to generate a first LLR value for a first variable node using first and second row update values for the first variable node. An output is configured to provide a decoded message generated based the plurality of LLR values.

公开(公告)号：US09967057B1

公开(公告)日：2018-05-08

申请号：US15345353

申请日：2016-11-07

Applicant: Xilinx, Inc.

Inventor： Nihat E. Tunali ,  Michael Wu ,  Hai-Jo Tarn ,  Christopher H. Dick

IPC: H04L27/06 ,  H04L1/00 ,  G06F17/18

CPC classification number: H04L1/0045 ,  G06F17/10 ,  H04L25/067

Abstract: A method includes communicating data in a channel. Received symbols for the data correspond to points of a received symbol space respectively. First and second dimensions of the received symbol space correspond to a real part and an imaginary part of the received symbols respectively. A first received symbol for the data is obtained. A first region of the received symbol space for the first received symbol is determined. A first regression model associated with the first region and a first bit of the first received symbol is retrieved from a storage. The first regression model includes a plurality of regressors. A first log-likelihood ratio (LLR) for the first bit of the first received symbol is estimated using the first regression model.

公开(公告)号：US09876657B1

公开(公告)日：2018-01-23

申请号：US15451209

申请日：2017-03-06

Applicant: Xilinx, Inc.

Inventor： Charles Jeon ,  Christoph E. Studer ,  Michael Wu ,  Christopher H. Dick

IPC: H04K1/02 ,  H04L25/03 ,  H04L25/49 ,  H04B7/0452

CPC classification number: H04L25/03159 ,  H04B7/0452 ,  H04L25/03012 ,  H04L2025/03426

Abstract: An integrated circuit (IC) includes a downlink unit including an input to receive a first plurality of frequency domain (FD) symbols associated with data symbols for a plurality of users, and an iteration unit to perform a plurality of iterations based on adjustment values. Each iteration includes generating a second plurality of FD symbols by performing a precoding process based on the first plurality of FD symbols, generating a third plurality of time domain (TD) symbols by performing a first modulation process based on the second plurality of FD symbols, generating a fourth plurality of TD symbols by performing a dynamic range reduction process based on absolute values of the third plurality of TD symbols, and updating the adjustment values. The downlink unit further includes a decision unit configured to generate transmit TD symbols for transmission through a channel to the plurality of users.

公开(公告)号：US09866269B1

公开(公告)日：2018-01-09

申请号：US15354858

申请日：2016-11-17

Applicant: Xilinx, Inc.

Inventor： Hongzhi Zhao ,  Christopher H. Dick ,  Hemang M. Parekh

IPC: H04B1/62 ,  H04L25/03

CPC classification number: H04B1/62 ,  H03F1/3247 ,  H03F1/3252 ,  H03F1/3258 ,  H03F3/195 ,  H03F3/245 ,  H03F2201/3209 ,  H03F2201/3224 ,  H03F2201/3233 ,  H04L25/03847

Abstract: A digital predistortion (DPD) system includes an input configured to receive a DPD input signal. The DPD system includes a first predistortion circuit configured to provide a first signal path coupled to the input to generate a first predistortion signal. The first predistortion circuit includes a first infinite impulse response (IIR) filter. A second predistortion circuit is configured to provide a second signal path coupled to the input in parallel with the first signal path to generate a second predistortion signal. The second predistortion circuit includes a second IIR filter. A combiner circuit is configured to combine the first predistortion signal and the second predistortion signal to generate a DPD output signal.

公开(公告)号：US09525470B1

公开(公告)日：2016-12-20

申请号：US14887186

申请日：2015-10-19

Applicant: Xilinx, Inc.

Inventor： Michael Wu ,  Christopher H. Dick ,  Christoph E. Studer

IPC: H04B7/04 ,  H04L5/00

CPC classification number: H04B7/0456 ,  H04B7/0452 ,  H04L5/0023

Abstract: A system includes a memory and an integrated circuit coupled to the memory. The integrated circuit is configured to communicate data in a channel characterized as a space having at least a frequency dimension. Anchor locations within the space correspond to respective regions of the space. The integrated circuit is further configured to determine a first inverse of a first matrix that corresponds to a first channel matrix for a first anchor location of the anchor locations. The first anchor location corresponds to a first region of the regions. The integrated circuit is further configured to perform an access link process for a second location other than the first anchor location but within the first region, the access link process using the first inverse determined for the first anchor location.

Abstract translation: 系统包括存储器和耦合到存储器的集成电路。 集成电路被配置为在特征为具有至少频率维度的空间的信道中传送数据。 空间内的锚定位置对应于空间的相应区域。 集成电路还被配置为确定对应于锚位置的第一锚定位置的第一信道矩阵的第一矩阵的第一逆。 第一锚定位置对应于区域的第一区域。 集成电路还被配置为对除第一锚定位置之外但在第一区域内的第二位置执行接入链路处理，该接入链路处理使用为第一锚定位置确定的第一个反相。