公开(公告)号：US06400022B1

公开(公告)日：2002-06-04

申请号：US09907689

申请日：2001-07-19

申请人： Takeshi Kishida ,  Shigenori Kido

发明人： Takeshi Kishida ,  Shigenori Kido

IPC分类号： H01L2840

CPC分类号： H01L21/76838 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91

摘要： A semiconductor device with a high reliability is provided. The semiconductor device includes a silicon substrate, titanium nitride films and an interlayer insulating film. A first opening is formed in the titanium nitride film. A second opening having a diameter different from that of the first opening is formed in the second titanium nitride film. A contact hole is formed in the interlayer insulating film. A titanium film, a titanium nitride film, a plug layer and an interconnect layer are formed so as to be electrically connected to the titanium nitride films through the first and second openings.

摘要翻译： 提供了具有高可靠性的半导体器件。 该半导体器件包括硅衬底，氮化钛膜和层间绝缘膜。 在氮化钛膜中形成第一开口。 在第二氮化钛膜中形成具有与第一开口的直径不同的直径的第二开口。 在层间绝缘膜中形成接触孔。 形成钛膜，氮化钛膜，插塞层和互连层，以通过第一和第二开口与氮化钛膜电连接。

公开(公告)号：US06251741B1

公开(公告)日：2001-06-26

申请号：US09219786

申请日：1998-12-23

申请人： Akinori Kinugasa ,  Tomoharu Mametani ,  Yukihiro Nagai ,  Hiroaki Nishimura ,  Takeshi Kishida

发明人： Akinori Kinugasa ,  Tomoharu Mametani ,  Yukihiro Nagai ,  Hiroaki Nishimura ,  Takeshi Kishida

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： There is described the manufacture of a semiconductor device having a storage node or high-yield manufacture of a compact memory IC. The present invention provides a method of manufacturing a semiconductor device including a basic dielectric layer formation step for forming a basic dielectric layer from a first dielectric material, a stopper film formation step for forming on the basic dielectric layer an etch stopper film from a second dielectric material differing from the first dielectric film, a sacrificial dielectric layer formation step for forming on the etch stopper film a sacrificial dielectric layer from the first dielectric material, a space formation step for forming a storage node formation space by removal of a predetermined area from the sacrificial dielectric layer until the etch stopper film becomes exposed, a storage node formation step for forming in the storage node formation space a storage node from a capacitive material, and a sacrificial dielectric layer removal step for removing the sacrificial dielectric layer surrounding the storage node by means of an etching operation suitable for removal of the first dielectric material.

摘要翻译： 描述了具有存储节点或紧凑型存储器IC的高产量制造的半导体器件的制造。 本发明提供一种制造半导体器件的方法，该半导体器件包括用于从第一介电材料形成基本电介质层的基本电介质层形成步骤，用于在基本电介质层上形成来自第二电介质的蚀刻停止膜的阻挡膜形成步骤 与第一介电膜不同的材料;牺牲介电层形成步骤，用于在蚀刻停止膜上形成来自第一介电材料的牺牲介电层;空间形成步骤，用于通过从第一电介质膜去除预定区域形成存储节点形成空间; 牺牲电介质层，直到蚀刻停止膜露出，存储节点形成步骤，用于在存储节点形成空间中形成存储节点与电容材料;以及牺牲介电层去除步骤，用于通过以下步骤去除存储节点周围的牺牲介电层： 蚀刻操作的手段适合于去除 l的第一介电材料。

公开(公告)号：US08443173B2

公开(公告)日：2013-05-14

申请号：US13153035

申请日：2011-06-03

申请人： Takeshi Kishida ,  Masaitsu Nakajima

发明人： Takeshi Kishida ,  Masaitsu Nakajima

IPC分类号： G06F9/30

CPC分类号： G06F9/30149 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3822 ,  G06F9/384 ,  G06F9/3853

摘要： A data processor which executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.

摘要翻译： 执行以第一和第二指令格式描述的指令的数据处理器。 第一指令格式定义了预定大小的寄存器寻址字段，而第二指令格式定义了大于由第一指令格式定义的寄存器寻址字段的大小的寄存器寻址字段。 数据处理器包括：指令类型标识符，响应于指令，用于通过指令本身识别接收到的以第一或第二指令格式描述的指令; 包括多个寄存器的第一寄存器堆; 以及还包括多个寄存器的第二寄存器堆，包括在第二寄存器堆中的寄存器的数目大于包含在第一寄存器堆中的寄存器的寄存器数。

公开(公告)号：US20090146273A1

公开(公告)日：2009-06-11

申请号：US11997700

申请日：2006-07-28

申请人： Yutaka Yamada ,  Takeshi Kishida ,  Yoshikazu Tamura ,  Yasuo Sogawa ,  Masanori Hirofuji

发明人： Yutaka Yamada ,  Takeshi Kishida ,  Yoshikazu Tamura ,  Yasuo Sogawa ,  Masanori Hirofuji

IPC分类号： H01L23/495

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06153 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48599 ,  H01L2224/49113 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00

摘要： There is provided a semiconductor device adopting, as a layout of pads connected to an external package on an LSI, a zigzag pad layout in which the pads are arranged shifted alternately, which can avoid occurrences of short-circuiting of wires, an increase in chip size due to avoidance of short-circuiting, propagation of power supply or GND noise due to reduction in IO cell interval, and signal transmission delay difference due to displacement of pad positions.In a semiconductor device wherein plural pads on a semiconductor element which are connected to function terminals on an external package are arranged in two lines along the periphery of the semiconductor element, an arrangement order of the plural pads on the semiconductor element is made different from an arrangement order of the function terminals on the external package.

摘要翻译： 提供了一种半导体器件，其采用连接到LSI上的外部封装的焊盘的布局，其中焊盘布置移位的之字形焊盘布局，这可以避免导线短路的发生，芯片的增加 由于避免短路，由于IO单元间隔的减少而导致的电源传播或GND噪声，以及由于焊盘位置的位移引起的信号传输延迟差异。 在半导体装置中，与外部封装上的功能端子连接的半导体元件上的多个焊盘沿着半导体元件的周边配置成两列，半导体元件上的多个焊盘的排列顺序与 功能端子在外部封装上的布置顺序。

公开(公告)号：US20070272963A1

公开(公告)日：2007-11-29

申请号：US11807494

申请日：2007-05-29

申请人： Takeshi Kishida

发明人： Takeshi Kishida

IPC分类号： H01L29/94 ,  H01L21/8242

CPC分类号： H01L27/10894 ,  H01L27/10852 ,  H01L28/91

摘要： A semiconductor device having in a deep hole formed in a first interlayer insulating film a memory cell region that comprises a plurality of capacitors having a lower electrode 229 composed of a crown structure having an outside face and inner face, a first upper electrode 231 facing the outside face of the lower electrode, and a dielectric and a second upper electrode extending from the inner face of the lower electrode to the surface of a first interlayer insulating film other than the deep hole; wherein the first upper electrode is connected to the second upper electrode by connecting a first upper electrode 227 formed on the inner wall of the deep hole to the wiring 241a via a conductor film 224 and a conductor plug 236a, and connecting a second upper electrode 231 to be a plate to a wiring 241a via a conductor plug 239a.

摘要翻译： 一种在第一层间绝缘膜中形成有深孔的半导体器件，存储单元区域包括具有由具有外表面和内表面的表冠结构构成的下电极229的多个电容器，面向 下电极的外表面以及从下电极的内表面延伸到除了深孔以外的第一层间绝缘膜的表面的电介质和第二上电极; 其中，所述第一上部电极通过经由导体膜224和导体插塞236a将形成在深孔的内壁上的第一上部电极227与布线241a连接而与第二上部电极连接，并且将第二上部电极 电极231经由导体插塞239a成为布线241a的板。

公开(公告)号：US20070150704A1

公开(公告)日：2007-06-28

申请号：US11706333

申请日：2007-02-15

申请人： Takeshi Kishida ,  Masaitsu Nakajima

发明人： Takeshi Kishida ,  Masaitsu Nakajima

IPC分类号： G06F9/40

CPC分类号： G06F9/30149 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3822 ,  G06F9/384 ,  G06F9/3853

摘要： A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file. If the instruction-type identifier has identified the received instruction as being described in the first instruction format, the data processor executes the instruction using data held in the first register file. On the other hand, if the instruction-type identifier has identified the received instruction as being described in the second instruction format, the data processor executes the instruction using data held in the second register file.

公开(公告)号：US06775920B2

公开(公告)日：2004-08-17

申请号：US10437911

申请日：2003-05-15

申请人： Takeshi Kishida ,  Shigenori Kido

发明人： Takeshi Kishida ,  Shigenori Kido

IPC分类号： G01D2100

CPC分类号： H01L23/544 ,  G03F7/70633 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A photolithography step is carried out for exposing/etching a resist film in an etching step. Thereafter a superposition inspection step employing a superposed layer superposition mark and a resist film superposition mark is carried out with a superposition inspection apparatus. In this step, an applied mask confirmation step is simultaneously carried out with the superposition inspection apparatus. Thus, it is possible to provide a method of fabricating a semiconductor device including a superposition inspection step, capable of efficiently confirming an applied mask and improving the fabrication yield for the semiconductor device.

摘要翻译： 在蚀刻步骤中进行曝光/蚀刻抗蚀剂膜的光刻步骤。 此后，使用重叠检查装置进行使用叠加层叠加标记和抗蚀剂膜叠加标记的叠加检查步骤。 在该步骤中，与叠加检查装置同时进行应用的掩模确认步骤。 因此，可以提供一种制造包括叠加检查步骤的半导体器件的方法，其能够有效地确认所施加的掩模并且提高半导体器件的制造成品率。

公开(公告)号：US06199155B1

公开(公告)日：2001-03-06

申请号：US09267135

申请日：1999-03-11

申请人： Takeshi Kishida ,  Masaitsu Nakajima

发明人： Takeshi Kishida ,  Masaitsu Nakajima

IPC分类号： G06F930

CPC分类号： G06F9/30149 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3822 ,  G06F9/384 ,  G06F9/3853

摘要： A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file. If the instruction-type identifier has identified the received instruction as being described in the first instruction format, the data processor executes the instruction using data held in the first register file. On the other hand, if the instruction-type identifier has identified the received instruction as being described in the second instruction format, the data processor executes the instruction using data held in the second register file.

公开(公告)号：US6065112A

公开(公告)日：2000-05-16

申请号：US98448

申请日：1998-06-17

申请人： Takeshi Kishida ,  Masaitsu Nakajima

发明人： Takeshi Kishida ,  Masaitsu Nakajima

IPC分类号： G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F9/302

CPC分类号： G06F9/3885 ,  G06F9/3017 ,  G06F9/325 ,  G06F9/3808 ,  G06F9/381

摘要： Along with an arithmetic processing unit and an arithmetic execution unit, another arithmetic processing unit is coupled in parallel to an instruction issue unit. Disposed within one of the arithmetic processing units are an address generation unit, an instruction buffer, an instruction decoder, an arithmetic execution unit, a data memory, and a flag register. The instruction decoder decodes an instruction read from the instruction buffer. If the decoded instruction is an iteration start instruction, the instruction decoder extracts a number of times an iterative process is to be executed that is included in the instruction for forwarding to the address generation unit. The address generation unit exerts control as to the execution and termination of iterative processes.

摘要翻译： 与算术处理单元和算术执行单元一起，另一个运算处理单元与指令发行单元并联耦合。 在一个运算处理单元内配置有地址生成单元，指令缓冲器，指令译码器，运算执行单元，数据存储器以及标志寄存器。 指令解码器对从指令缓冲器读取的指令进行解码。 如果解码指令是迭代开始指令，则指令解码器提取包括在用于转发到地址生成单元的指令中的要执行的迭代处理的次数。 地址生成单元对迭代处理的执行和终止进行控制。