公开(公告)号：US07829983B2

公开(公告)日：2010-11-09

申请号：US11997700

申请日：2006-07-28

申请人： Yutaka Yamada ,  Takeshi Kishida ,  Yoshikazu Tamura ,  Yasuo Sogawa ,  Masanori Hirofuji

发明人： Yutaka Yamada ,  Takeshi Kishida ,  Yoshikazu Tamura ,  Yasuo Sogawa ,  Masanori Hirofuji

IPC分类号： H01L23/495

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06153 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48599 ,  H01L2224/49113 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00

摘要： There is provided a semiconductor device adopting, as a layout of pads connected to an external package on an LSI, a zigzag pad layout in which the pads are arranged shifted alternately, which can avoid occurrences of short-circuiting of wires, an increase in chip size due to avoidance of short-circuiting, propagation of power supply or GND noise due to reduction in IO cell interval, and signal transmission delay difference due to displacement of pad positions. In a semiconductor device wherein plural pads on a semiconductor element which are connected to function terminals on an external package are arranged in two lines along the periphery of the semiconductor element, an arrangement order of the plural pads on the semiconductor element is different from an arrangement order of the function terminals on the external package.

摘要翻译： 提供了一种半导体器件，其采用连接到LSI上的外部封装的焊盘的布局，其中焊盘布置移位的之字形焊盘布局，这可以避免导线短路的发生，芯片的增加 由于避免短路，由于IO单元间隔的减少而导致的电源传播或GND噪声，以及由于焊盘位置的位移引起的信号传输延迟差异。 在半导体装置中，与外部封装上的功能端子连接的半导体元件上的多个焊盘沿着半导体元件的周边配置成两列，半导体元件上的多个焊盘的配置顺序与布置 外部封装上功能端子的顺序。

公开(公告)号：US06337268B1

公开(公告)日：2002-01-08

申请号：US09610701

申请日：2000-07-05

申请人： Shigenori Kido ,  Jiro Matsufusa ,  Tomoharu Mametani ,  Yoji Nakata ,  Takeshi Kishida ,  Yukihiro Nagai ,  Akinori Kinugasa ,  Hiroaki Nishimura

发明人： Shigenori Kido ,  Jiro Matsufusa ,  Tomoharu Mametani ,  Yoji Nakata ,  Takeshi Kishida ,  Yukihiro Nagai ,  Akinori Kinugasa ,  Hiroaki Nishimura

IPC分类号： H01L214763

CPC分类号： H01L21/76801 ,  H01L21/76804

摘要： A contact structure is formed with no voids in an interlayer insulation film and good surface planarity. A first insulation film (21) formed of p-TEOS is deposited to cover a substrate (1) and wires (4) formed on the substrate (1). A second insulation film (22) which is coating glass is formed by SOG. The surface is etched back from the opposite side to the substrate (1); therefore, the second insulation film (22) is etched. The etching is stopped at the point where the surface (21a) of the first insulation film (21) on the wires (4) is exposed. This ensures good surface,planarity. A third insulation film (23) is stacked on top of the second insulation film (22), and portions of the third insulation film (23) above the wires (4) are isotropically etched to form openings (51). At this time, the isotropic etching does not extend over the second insulation film (22).

摘要翻译： 在层间绝缘膜中形成没有空隙的接触结构和良好的表面平面度。 沉积由p-TEOS形成的第一绝缘膜（21）以覆盖基板（1）和形成在基板（1）上的布线（4）。 涂覆玻璃的第二绝缘膜（22）由SOG形成。 表面从衬底（1）的相对侧被回蚀刻; 因此，蚀刻第二绝缘膜（22）。 蚀刻停止在电线（4）上的第一绝缘膜（21）的表面（21a）露出的点处。 这确保了良好的表面，平坦度。 第三绝缘膜（23）层叠在第二绝缘膜（22）的顶部上，并且将各导线（4）上方的第三绝缘膜（23）的各部分各向同性地蚀刻以形成开口（51）。 此时，各向同性蚀刻不会延伸超过第二绝缘膜（22）。

公开(公告)号：US08564037B2

公开(公告)日：2013-10-22

申请号：US13012305

申请日：2011-01-24

申请人： Takeshi Kishida

发明人： Takeshi Kishida

IPC分类号： H01L27/108

CPC分类号： H01L21/76224 ,  H01L29/06

摘要： A semiconductor device may include, but is not limited to, a semiconductor substrate having a device isolation groove defining first to fourth device formation portions. The second device formation portion is separated from the first device formation portion. The third device formation portion extends from the first device formation portion. The third device formation portion is separated from the second device formation portion. The fourth device formation portion extends from the second device formation portion. The fourth device formation portion is separated from the first and third device formation portions. The third and fourth device formation portions are positioned between the first and second device formation portions.

摘要翻译： 半导体器件可以包括但不限于具有限定第一至第四器件形成部分的器件隔离槽的半导体衬底。 第二装置形成部分与第一装置形成部分分离。 第三装置形成部分从第一装置形成部分延伸。 第三装置形成部分与第二装置形成部分分离。 第四装置形成部分从第二装置形成部分延伸。 第四装置形成部分与第一和第三装置形成部分分离。 第三和第四装置形成部分位于第一和第二装置形成部分之间。

公开(公告)号：US07194602B2

公开(公告)日：2007-03-20

申请号：US10385854

申请日：2003-03-12

申请人： Takeshi Kishida ,  Masaitsu Nakajima

发明人： Takeshi Kishida ,  Masaitsu Nakajima

IPC分类号： G06F9/34 ,  G06F9/355

CPC分类号： G06F9/30149 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3822 ,  G06F9/384 ,  G06F9/3853

摘要： A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file. If the instruction-type identifier has identified the received instruction as being described in the first instruction format, the data processor executes the instruction using data held in the first register file. On the other hand, if the instruction-type identifier has identified the received instruction as being described in the second instruction format, the data processor executes the instruction using data held in the second register file.

摘要翻译： 根据本发明的数据处理器执行以第一和第二指令格式描述的指令。 第一指令格式定义了预定大小的寄存器寻址字段，而第二指令格式定义了大于由第一指令格式定义的寄存器寻址字段的大小的寄存器寻址字段。 数据处理器包括：指令类型标识符，响应于指令，用于通过指令本身识别接收到的以第一或第二指令格式描述的指令; 包括多个寄存器的第一寄存器堆; 以及还包括多个寄存器的第二寄存器堆，包括在第二寄存器堆中的寄存器的数目大于包含在第一寄存器堆中的寄存器的寄存器数。 如果指令类型标识符已经将接收到的指令识别为如第一指令格式所描述的那样，则数据处理器使用保存在第一寄存器文件中的数据来执行指令。 另一方面，如果指令类型标识符已经将接收到的指令识别为如第二指令格式所描述的那样，则数据处理器使用保存在第二寄存器堆中的数据来执行指令。

公开(公告)号：US06977199B2

公开(公告)日：2005-12-20

申请号：US10900151

申请日：2004-07-28

申请人： Takeshi Kishida ,  Yusuke Kawase

发明人： Takeshi Kishida ,  Yusuke Kawase

IPC分类号： H01L21/8242 ,  H01L21/02 ,  H01L27/108

CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/84

摘要： On a silicon oxide film including the interior of an opening a semispherical RGP film is deposited. At a temperature lower than that allowing a crystal of silicon to be grown a BPTEOS film is deposited to fill the opening. Then a portion other than the semispherical RGP film introduced in the opening is chemically mechanically polished and thus removed. This contributes to reduced crystal growth of silicon at the semispherical RGP film and hence reduced scattering and/or removal of the RGP film for example when a CMP step is performed. Subsequently the semispherical RGP film is annealed to grow a crystal of silicon to form a generally spherical RGP film. Thus a storage node can have an increased surface area and a capacitor can have increased capacity.

摘要翻译： 在包含开口内部的氧化硅膜上沉积半球形RGP膜。 在低于允许生长硅晶体的温度下，沉积BPTEOS膜以填充开口。 然后将引入到开口中的半球形RGP膜以外的部分化学机械抛光并因此被除去。 这有助于在半球形RGP膜处降低硅的晶体生长，并因此例如当执行CMP步骤时减少RGP膜的散射和/或去除。 随后将半球形RGP膜退火以生长硅晶体，以形成通常为球形的RGP膜。 因此，存储节点可以具有增加的表面积，并且电容器可以具有增加的容量。

公开(公告)号：US06787878B1

公开(公告)日：2004-09-07

申请号：US09631623

申请日：2000-08-04

申请人： Yukihiro Nagai ,  Tomoharu Mametani ,  Yoji Nakata ,  Shigenori Kido ,  Takeshi Kishida ,  Akinori Kinugasa ,  Hiroaki Nishimura ,  Jiro Matsufusa

发明人： Yukihiro Nagai ,  Tomoharu Mametani ,  Yoji Nakata ,  Shigenori Kido ,  Takeshi Kishida ,  Akinori Kinugasa ,  Hiroaki Nishimura ,  Jiro Matsufusa

IPC分类号： H01L2900

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor device, an active region is formed in a semiconductor substrate separated by a plurality of isolation regions. A plurality of surface insulating films of different thickness are formed separately on the active region. A plurality of conductive films are formed on the respective insulating films. Then, one of the surface insulating film having smaller thickness is caused to break down to work as an electric fuse.

摘要翻译： 在半导体器件中，有源区形成在由多个隔离区隔开的半导体衬底中。 在活性区域上分别形成多个不同厚度的表面绝缘膜。 在各绝缘膜上形成多个导电膜。 然后，使具有较小厚度的表面绝缘膜中的一个分解成电熔丝。

公开(公告)号：US06549999B2

公开(公告)日：2003-04-15

申请号：US09761177

申请日：2001-01-18

申请人： Takeshi Kishida ,  Masaitsu Nakajima

发明人： Takeshi Kishida ,  Masaitsu Nakajima

IPC分类号： G06F930

CPC分类号： G06F9/30149 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3822 ,  G06F9/384 ,  G06F9/3853

摘要： A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file. If the instruction-type identifier has identified the received instruction as being described in the first instruction format, the data processor executes the instruction using data held in the first register file. On the other hand, if the instruction-type identifier has identified the received instruction as being described in the second instruction format, the data processor executes the instruction using data held in the second register file.

摘要翻译： 根据本发明的数据处理器执行以第一和第二指令格式描述的指令。 第一指令格式定义了预定大小的寄存器寻址字段，而第二指令格式定义了大于由第一指令格式定义的寄存器寻址字段的大小的寄存器寻址字段。 数据处理器包括：指令类型标识符，响应于指令，用于通过指令本身识别接收到的以第一或第二指令格式描述的指令; 包括多个寄存器的第一寄存器堆; 以及还包括多个寄存器的第二寄存器堆，包括在第二寄存器堆中的寄存器的数目大于包含在第一寄存器堆中的寄存器的寄存器数。 如果指令类型标识符已经将接收到的指令识别为如第一指令格式所描述的那样，则数据处理器使用保存在第一寄存器文件中的数据来执行指令。 另一方面，如果指令类型标识符已经将接收到的指令识别为如第二指令格式所描述的那样，则数据处理器使用保存在第二寄存器堆中的数据来执行指令。

公开(公告)号：US06348950B1

公开(公告)日：2002-02-19

申请号：US09379209

申请日：1999-08-20

申请人： Takeshi Kishida

发明人： Takeshi Kishida

IPC分类号： H04N701

CPC分类号： H04N7/0135 ,  H04N7/0105 ,  H04N9/64

摘要： This invention relates to a video signal processing circuit for easily simultaneously performing conversion of the number of lines and format conversion with a simple construction and an image pickup apparatus such as CCD using the circuit. A signal in a 4:2:2 format is supplied to a linear interpolating unit. Input luminance signals and input color difference signals of one line are written into line memories and the input luminance signals and the input color difference signals of the next one line are written into other memories. Similarly, signals are alternately written. The input luminance signal is read twice from the above memories in a period of writing signals of one line. The obtained signals are multiplied by coefficients for linear interpolation, respectively, and the resultant signals are added, thereby generating a luminance signal to be outputted. At the occasion of reading the input luminance signal twice, the input color difference signal is read once from the above memories and multiplied by each of coefficients, and the resultant signals are added, thereby generating a color difference signal to be outputted. A writing/reading control of a signal to/from memories and setting of the coefficients are performed by an interpolation control unit. Thus, the number of lines can be changed in a real time manner and the signal can be converted into a signal in a 4:2:0 format.

摘要翻译： 本发明涉及一种视频信号处理电路，用于利用简单的结构容易地同时执行行数转换和格式转换，以及使用该电路的诸如CCD的图像拾取装置。 4：2：2格式的信号被提供给线性插值单元。 将一行的输入亮度信号和输入色差信号写入行存储器，并将下一行的输入亮度信号和输入色差信号写入其他存储器。 类似地，信号被交替写入。 在一行的写入信号的周期中，从上述存储器读入输入亮度信号两次。 将所获得的信号分别乘以用于线​​性插值的系数，并将所得到的信号相加，从而生成要输出的亮度信号。 在读取输入亮度信号两次的情况下，输入色差信号从上述存储器中读取一次，并乘以每个系数，并将所得到的信号相加，从而产生要输出的色差信号。 通过插值控制单元执行对存储器的信号的写入/读取控制和系数的设置。 因此，可以实时地改变行数，并且可以将信号转换为4：2：0格式的信号。

公开(公告)号：US07969470B2

公开(公告)日：2011-06-28

申请号：US11377004

申请日：2006-03-16

申请人： Takeshi Kishida

发明人： Takeshi Kishida

IPC分类号： H04N5/228

CPC分类号： G06K9/6218 ,  G06K9/00771 ,  G06T7/231 ,  G06T2207/10016 ,  G06T2207/30232

摘要： A moving object detection device accurately detects moving objects. The device includes a motion vector calculation section calculating motion vectors from an input image; a motion vector removal section removing a motion vector having high randomness from the calculated motion vectors; a motion vector accumulation section temporally accumulating each motion vector not removed by the motion vector removal section, and calculating an accumulated number of occurrences and an accumulated value of each motion vector; and a moving object detection section determining, based on the calculated accumulated value and calculated accumulated number of occurrences of each motion vector, whether each motion vector corresponds to a moving object.

摘要翻译： 运动物体检测装置精确地检测运动物体。 该装置包括运动矢量计算部分，用于从输入图像计算运动矢量; 运动矢量去除部分，从计算出的运动矢量中去除具有高随机性的运动矢量; 运动矢量累积部分，其时间上累积由运动矢量除去部分未被去除的每个运动矢量，并且计算累积的出现次数和每个运动矢量的累积值; 以及运动对象检测部，其基于计算出的累积值和计算出的每个运动矢量的累计出现次数来确定每个运动矢量是否对应于运动对象。

公开(公告)号：US20110012245A1

公开(公告)日：2011-01-20

申请号：US12892165

申请日：2010-09-28

申请人： Yutaka YAMADA ,  Takeshi Kishida ,  Yoshikazu Tamura ,  Yasuo Sogawa ,  Masanori Hirofuji

发明人： Yutaka YAMADA ,  Takeshi Kishida ,  Yoshikazu Tamura ,  Yasuo Sogawa ,  Masanori Hirofuji

IPC分类号： H01L23/528

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06153 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48599 ,  H01L2224/49113 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00

摘要： There is provided a semiconductor device adopting, as a layout of pads connected to an external package on an LSI, a zigzag pad layout in which the pads are arranged shifted alternately, which can avoid occurrences of short-circuiting of wires, an increase in chip size due to avoidance of short-circuiting, propagation of power supply or GND noise due to reduction in IO cell interval, and signal transmission delay difference due to displacement of pad positions. In a semiconductor device wherein plural pads on a semiconductor element which are connected to function terminals on an external package are arranged in two lines along the periphery of the semiconductor element, an arrangement order of the plural pads on the semiconductor element is different from an arrangement order of the function terminals on the external package.

摘要翻译： 提供了一种半导体器件，其采用连接到LSI上的外部封装的焊盘的布局，其中焊盘布置移位的之字形焊盘布局，这可以避免导线短路的发生，芯片的增加 由于避免短路，由于IO单元间隔的减少而导致的电源传播或GND噪声，以及由于焊盘位置的位移引起的信号传输延迟差异。 在半导体装置中，与外部封装上的功能端子连接的半导体元件上的多个焊盘沿着半导体元件的周边配置成两列，半导体元件上的多个焊盘的配置顺序与布置 外部封装上功能端子的顺序。