公开(公告)号：US07979676B2

公开(公告)日：2011-07-12

申请号：US12632532

申请日：2009-12-07

申请人： Takeshi Kishida ,  Masaitsu Nakajima

发明人： Takeshi Kishida ,  Masaitsu Nakajima

IPC分类号： G06F9/30

CPC分类号： G06F9/30149 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3822 ,  G06F9/384 ,  G06F9/3853

摘要： A data processor which executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.

摘要翻译： 执行以第一和第二指令格式描述的指令的数据处理器。 第一指令格式定义了预定大小的寄存器寻址字段，而第二指令格式定义了大于由第一指令格式定义的寄存器寻址字段的大小的寄存器寻址字段。 数据处理器包括：指令类型标识符，响应于指令，用于通过指令本身识别接收到的以第一或第二指令格式描述的指令; 包括多个寄存器的第一寄存器堆; 以及还包括多个寄存器的第二寄存器堆，包括在第二寄存器堆中的寄存器的数目大于包含在第一寄存器堆中的寄存器的寄存器数。

公开(公告)号：US07194602B2

公开(公告)日：2007-03-20

申请号：US10385854

申请日：2003-03-12

申请人： Takeshi Kishida ,  Masaitsu Nakajima

发明人： Takeshi Kishida ,  Masaitsu Nakajima

IPC分类号： G06F9/34 ,  G06F9/355

CPC分类号： G06F9/30149 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3822 ,  G06F9/384 ,  G06F9/3853

摘要： A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file. If the instruction-type identifier has identified the received instruction as being described in the first instruction format, the data processor executes the instruction using data held in the first register file. On the other hand, if the instruction-type identifier has identified the received instruction as being described in the second instruction format, the data processor executes the instruction using data held in the second register file.

摘要翻译： 根据本发明的数据处理器执行以第一和第二指令格式描述的指令。 第一指令格式定义了预定大小的寄存器寻址字段，而第二指令格式定义了大于由第一指令格式定义的寄存器寻址字段的大小的寄存器寻址字段。 数据处理器包括：指令类型标识符，响应于指令，用于通过指令本身识别接收到的以第一或第二指令格式描述的指令; 包括多个寄存器的第一寄存器堆; 以及还包括多个寄存器的第二寄存器堆，包括在第二寄存器堆中的寄存器的数目大于包含在第一寄存器堆中的寄存器的寄存器数。 如果指令类型标识符已经将接收到的指令识别为如第一指令格式所描述的那样，则数据处理器使用保存在第一寄存器文件中的数据来执行指令。 另一方面，如果指令类型标识符已经将接收到的指令识别为如第二指令格式所描述的那样，则数据处理器使用保存在第二寄存器堆中的数据来执行指令。

公开(公告)号：US06549999B2

公开(公告)日：2003-04-15

申请号：US09761177

申请日：2001-01-18

申请人： Takeshi Kishida ,  Masaitsu Nakajima

发明人： Takeshi Kishida ,  Masaitsu Nakajima

IPC分类号： G06F930

CPC分类号： G06F9/30149 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3822 ,  G06F9/384 ,  G06F9/3853

摘要： A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file. If the instruction-type identifier has identified the received instruction as being described in the first instruction format, the data processor executes the instruction using data held in the first register file. On the other hand, if the instruction-type identifier has identified the received instruction as being described in the second instruction format, the data processor executes the instruction using data held in the second register file.

摘要翻译： 根据本发明的数据处理器执行以第一和第二指令格式描述的指令。 第一指令格式定义了预定大小的寄存器寻址字段，而第二指令格式定义了大于由第一指令格式定义的寄存器寻址字段的大小的寄存器寻址字段。 数据处理器包括：指令类型标识符，响应于指令，用于通过指令本身识别接收到的以第一或第二指令格式描述的指令; 包括多个寄存器的第一寄存器堆; 以及还包括多个寄存器的第二寄存器堆，包括在第二寄存器堆中的寄存器的数目大于包含在第一寄存器堆中的寄存器的寄存器数。 如果指令类型标识符已经将接收到的指令识别为如第一指令格式所描述的那样，则数据处理器使用保存在第一寄存器文件中的数据来执行指令。 另一方面，如果指令类型标识符已经将接收到的指令识别为如第二指令格式所描述的那样，则数据处理器使用保存在第二寄存器堆中的数据来执行指令。

公开(公告)号：US20100146244A1

公开(公告)日：2010-06-10

申请号：US12632532

申请日：2009-12-07

申请人： Takeshi Kishida ,  Masaitsu Nakajima

发明人： Takeshi Kishida ,  Masaitsu Nakajima

IPC分类号： G06F9/30

CPC分类号： G06F9/30149 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3822 ,  G06F9/384 ,  G06F9/3853

摘要： A data processor which executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.

摘要翻译： 执行以第一和第二指令格式描述的指令的数据处理器。 第一指令格式定义了预定大小的寄存器寻址字段，而第二指令格式定义了大于由第一指令格式定义的寄存器寻址字段的大小的寄存器寻址字段。 数据处理器包括：指令类型标识符，响应于指令，用于通过指令本身识别接收到的以第一或第二指令格式描述的指令; 包括多个寄存器的第一寄存器堆; 以及还包括多个寄存器的第二寄存器堆，包括在第二寄存器堆中的寄存器的数目大于包含在第一寄存器堆中的寄存器的寄存器数。

公开(公告)号：US07664934B2

公开(公告)日：2010-02-16

申请号：US11706333

申请日：2007-02-15

申请人： Takeshi Kishida ,  Masaitsu Nakajima

发明人： Takeshi Kishida ,  Masaitsu Nakajima

IPC分类号： G06F9/30

CPC分类号： G06F9/30149 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3822 ,  G06F9/384 ,  G06F9/3853

摘要： A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file. If the instruction-type identifier has identified the received instruction as being described in the first instruction format, the data processor executes the instruction using data held in the first register file. On the other hand, if the instruction-type identifier has identified the received instruction as being described in the second instruction format, the data processor executes the instruction using data held in the second register file.

摘要翻译： 根据本发明的数据处理器执行以第一和第二指令格式描述的指令。 第一指令格式定义了预定大小的寄存器寻址字段，而第二指令格式定义了大于由第一指令格式定义的寄存器寻址字段的大小的寄存器寻址字段。 数据处理器包括：指令类型标识符，响应于指令，用于通过指令本身识别接收到的以第一或第二指令格式描述的指令; 包括多个寄存器的第一寄存器堆; 以及还包括多个寄存器的第二寄存器堆，包括在第二寄存器堆中的寄存器的数目大于包含在第一寄存器堆中的寄存器的寄存器数。 如果指令类型标识符已经将接收到的指令识别为如第一指令格式所描述的那样，则数据处理器使用保存在第一寄存器文件中的数据来执行指令。 另一方面，如果指令类型标识符已经将接收到的指令识别为如第二指令格式所描述的那样，则数据处理器使用保存在第二寄存器堆中的数据来执行指令。

公开(公告)号：US08443173B2

公开(公告)日：2013-05-14

申请号：US13153035

申请日：2011-06-03

申请人： Takeshi Kishida ,  Masaitsu Nakajima

发明人： Takeshi Kishida ,  Masaitsu Nakajima

IPC分类号： G06F9/30

CPC分类号： G06F9/30149 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3822 ,  G06F9/384 ,  G06F9/3853

摘要： A data processor which executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.

摘要翻译： 执行以第一和第二指令格式描述的指令的数据处理器。 第一指令格式定义了预定大小的寄存器寻址字段，而第二指令格式定义了大于由第一指令格式定义的寄存器寻址字段的大小的寄存器寻址字段。 数据处理器包括：指令类型标识符，响应于指令，用于通过指令本身识别接收到的以第一或第二指令格式描述的指令; 包括多个寄存器的第一寄存器堆; 以及还包括多个寄存器的第二寄存器堆，包括在第二寄存器堆中的寄存器的数目大于包含在第一寄存器堆中的寄存器的寄存器数。

公开(公告)号：US20070150704A1

公开(公告)日：2007-06-28

申请号：US11706333

申请日：2007-02-15

申请人： Takeshi Kishida ,  Masaitsu Nakajima

发明人： Takeshi Kishida ,  Masaitsu Nakajima

IPC分类号： G06F9/40

CPC分类号： G06F9/30149 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3822 ,  G06F9/384 ,  G06F9/3853

摘要： A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file. If the instruction-type identifier has identified the received instruction as being described in the first instruction format, the data processor executes the instruction using data held in the first register file. On the other hand, if the instruction-type identifier has identified the received instruction as being described in the second instruction format, the data processor executes the instruction using data held in the second register file.

公开(公告)号：US06199155B1

公开(公告)日：2001-03-06

申请号：US09267135

申请日：1999-03-11

申请人： Takeshi Kishida ,  Masaitsu Nakajima

发明人： Takeshi Kishida ,  Masaitsu Nakajima

IPC分类号： G06F930

CPC分类号： G06F9/30149 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3822 ,  G06F9/384 ,  G06F9/3853

摘要： A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file. If the instruction-type identifier has identified the received instruction as being described in the first instruction format, the data processor executes the instruction using data held in the first register file. On the other hand, if the instruction-type identifier has identified the received instruction as being described in the second instruction format, the data processor executes the instruction using data held in the second register file.

公开(公告)号：US6065112A

公开(公告)日：2000-05-16

申请号：US98448

申请日：1998-06-17

申请人： Takeshi Kishida ,  Masaitsu Nakajima

发明人： Takeshi Kishida ,  Masaitsu Nakajima

IPC分类号： G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F9/302

CPC分类号： G06F9/3885 ,  G06F9/3017 ,  G06F9/325 ,  G06F9/3808 ,  G06F9/381

摘要： Along with an arithmetic processing unit and an arithmetic execution unit, another arithmetic processing unit is coupled in parallel to an instruction issue unit. Disposed within one of the arithmetic processing units are an address generation unit, an instruction buffer, an instruction decoder, an arithmetic execution unit, a data memory, and a flag register. The instruction decoder decodes an instruction read from the instruction buffer. If the decoded instruction is an iteration start instruction, the instruction decoder extracts a number of times an iterative process is to be executed that is included in the instruction for forwarding to the address generation unit. The address generation unit exerts control as to the execution and termination of iterative processes.

摘要翻译： 与算术处理单元和算术执行单元一起，另一个运算处理单元与指令发行单元并联耦合。 在一个运算处理单元内配置有地址生成单元，指令缓冲器，指令译码器，运算执行单元，数据存储器以及标志寄存器。 指令解码器对从指令缓冲器读取的指令进行解码。 如果解码指令是迭代开始指令，则指令解码器提取包括在用于转发到地址生成单元的指令中的要执行的迭代处理的次数。 地址生成单元对迭代处理的执行和终止进行控制。

公开(公告)号：US07829983B2

公开(公告)日：2010-11-09

申请号：US11997700

申请日：2006-07-28

申请人： Yutaka Yamada ,  Takeshi Kishida ,  Yoshikazu Tamura ,  Yasuo Sogawa ,  Masanori Hirofuji

发明人： Yutaka Yamada ,  Takeshi Kishida ,  Yoshikazu Tamura ,  Yasuo Sogawa ,  Masanori Hirofuji

IPC分类号： H01L23/495

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06153 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48599 ,  H01L2224/49113 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00

摘要： There is provided a semiconductor device adopting, as a layout of pads connected to an external package on an LSI, a zigzag pad layout in which the pads are arranged shifted alternately, which can avoid occurrences of short-circuiting of wires, an increase in chip size due to avoidance of short-circuiting, propagation of power supply or GND noise due to reduction in IO cell interval, and signal transmission delay difference due to displacement of pad positions. In a semiconductor device wherein plural pads on a semiconductor element which are connected to function terminals on an external package are arranged in two lines along the periphery of the semiconductor element, an arrangement order of the plural pads on the semiconductor element is different from an arrangement order of the function terminals on the external package.

摘要翻译： 提供了一种半导体器件，其采用连接到LSI上的外部封装的焊盘的布局，其中焊盘布置移位的之字形焊盘布局，这可以避免导线短路的发生，芯片的增加 由于避免短路，由于IO单元间隔的减少而导致的电源传播或GND噪声，以及由于焊盘位置的位移引起的信号传输延迟差异。 在半导体装置中，与外部封装上的功能端子连接的半导体元件上的多个焊盘沿着半导体元件的周边配置成两列，半导体元件上的多个焊盘的配置顺序与布置 外部封装上功能端子的顺序。