公开(公告)号：US20220293750A1

公开(公告)日：2022-09-15

申请号：US17501852

申请日：2021-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: H01L29/417 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8234 ,  H01L29/40 ,  H01L25/00

Abstract: An integrated circuit includes a first chip bonded to a second chip. The first chip includes gate all around transistors on a substrate. The first chip includes backside conductive vias extending through the substrate to the gate all around transistors. The second chip includes electronic circuitry electrically connected to the transistors by the backside conductive vias.

公开(公告)号：US20220228265A1

公开(公告)日：2022-07-21

申请号：US17150699

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: C23C16/52 ,  H01L21/02 ,  G05B13/04 ,  C23C16/458 ,  C23C16/455

Abstract: A thin-film deposition system deposits thin films on semiconductor wafers. The thin-film deposition system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for a next deposition process by receiving static process conditions and target thin-film data. The analysis model identifies dynamic process conditions data that, together with the static process conditions data, result in predicted thin-film data that matches the target thin-film data. The deposition system then uses the static and dynamic process conditions data for the next thin-film deposition process.

公开(公告)号：US20210408259A1

公开(公告)日：2021-12-30

申请号：US17194688

申请日：2021-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/66

Abstract: A device includes a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure includes a first dielectric layer over the semiconductor channel, a first work function metal layer over the first dielectric layer, a first protection layer over the first work function metal layer, a second protection layer over the first protection layer, and a metal fill layer over the second protection layer.

公开(公告)号：US20210143098A1

公开(公告)日：2021-05-13

申请号：US17156292

申请日：2021-01-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Shih Wei BIH ,  Yen-Yu CHEN

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105

Abstract: A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive structure and respective sidewalls of the one or more isolation layers, wherein the first conductive structure is electrically coupled to a second conductive structure through at least the bottom surface.

公开(公告)号：US20160362782A1

公开(公告)日：2016-12-15

申请号：US14739355

申请日：2015-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang CHENG ,  Wei ZHANG ,  Ching-Chia WU ,  Wei-Jen CHEN ,  Yen-Yu CHEN

IPC: C23C16/44 ,  C23C16/455 ,  C23C16/505

CPC classification number: C23C16/4404 ,  C23C16/4405 ,  C23C16/4408 ,  C23C16/45565 ,  C23C16/5096

Abstract: A gas dispenser utilized in a deposition apparatus is provided. The gas dispenser includes a showerhead comprising a plurality of holes, and a mask layer formed on a surface of the showerhead, wherein the holes penetrate through the mask layer. A deposition apparatus using the gas dispenser is also disclosed.

Abstract translation: 提供了用于沉积设备中的气体分配器。 气体分配器包括一个包括多个孔的喷头和形成在喷头表面上的掩模层，其中孔穿透掩模层。 还公开了一种使用气体分配器的沉积设备。

公开(公告)号：US20150147892A1

公开(公告)日：2015-05-28

申请号：US14092362

申请日：2013-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang CHENG ,  Chien-Hao TSENG ,  Yen-Yu CHEN ,  Ching-Chia WU ,  Chang-Sheng LEE ,  Wei ZHANG

IPC: H01L21/02 ,  C23C16/44 ,  H01L21/28

CPC classification number: C23C16/4402 ,  C23C16/4481 ,  C23C16/4485 ,  C23C16/45544 ,  C23C16/45553 ,  H01L21/28158 ,  H01L21/28167 ,  H01L21/28185 ,  H01L29/517

Abstract: A method for fabricating a semiconductor structure is provided, including: providing a solid precursor having a first average particle size; solving the solid precursor in an organic solvent into an intermediate; recrystallizing the intermediate to form solid granules, wherein the solid granules has a second average particle size larger than the first average particle size; vaporizing the solid granules to form a film-forming gas; and depositing the film-forming gas on a substrate to form a resistance film. A method for modifying a resistance film source in a semiconductor fabrication and a solid precursor delivery system are also provided. The method for fabricating a semiconductor structure in the present disclosure can remove small particles or ultra-small particles from solid precursor, and does not need extra time to dump cracked solid precursor.

Abstract translation: 提供一种制造半导体结构的方法，包括：提供具有第一平均粒度的固体前体; 将有机溶剂中的固体前体溶解成中间体; 使中间体重结晶形成固体颗粒，其中固体颗粒具有大于第一平均粒度的第二平均粒径; 蒸发固体颗粒以形成成膜气体; 并将成膜气体沉积在基板上以形成电阻膜。 还提供了一种用于修改半导体制造中的电阻膜源和固体前体输送系统的方法。 在本发明中制造半导体结构的方法可以从固体前驱物除去小颗粒或超小颗粒，并且不需要额外的时间来倾倒破裂的固体前体。

公开(公告)号：US20240379804A1

公开(公告)日：2024-11-14

申请号：US18784711

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: H01L29/423 ,  H01L27/12

Abstract: A semiconductor device includes a substrate, a gate all around (GAA) device overlying the substrate, and a thin film transistor (TFT) overlying the GAA device, and a passive device overlying the TFT. The substrate, the GAA device, the TFT, and the passive device is subsequently stacked on each other and at least partially overlap with each other. A via includes a first end, a second end, and a middle portion of the via that is located between the first end and the second end of the via. The first end of the via is connected to the passive device and the second end of the via is connected to one layer of the GAA device. The middle portion of the via is laterally spaced apart from the TFT and the passive device.

公开(公告)号：US20240088227A1

公开(公告)日：2024-03-14

申请号：US18516215

申请日：2023-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Chun-I WU ,  Huang-Lin CHAO

IPC: H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1037 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/785

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The method includes forming first and second nanostructured channel regions in first and second nanostructured layers, respectively, and forming first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The forming the first and second GAA structures includes selectively forming an Al-based n-type work function metal layer and a Si-based capping layer on the first nanostructured channel regions, depositing a bi-layer of Al-free p-type work function metal layers on the first and second nanostructured channel regions, depositing a fluorine blocking layer on the bi-layer of Al-free p-type work function layers, and depositing a gate metal fill layer on the fluorine blocking layer.

公开(公告)号：US20230363145A1

公开(公告)日：2023-11-09

申请号：US18352738

申请日：2023-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG

IPC: H10B12/00 ,  H01L21/02 ,  H01L21/225 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/94

CPC classification number: H10B12/33 ,  H01L21/02603 ,  H01L21/2251 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66181 ,  H01L29/66742 ,  H01L29/78696 ,  H01L29/94 ,  H10B12/05 ,  H10B12/036

Abstract: A device includes a substrate. A first nanostructure is over the substrate, and includes a semiconductor having a first resistance. A second nanostructure is over the substrate, is offset laterally from the first nanostructure, is at about the same height above the substrate as the first nanostructure, and includes a conductor having a second resistance lower than the first resistance. A first gate structure is over and wrapped around the first nanostructure, and a second gate structure is over and wrapped around the second nanostructure.

公开(公告)号：US20230187526A1

公开(公告)日：2023-06-15

申请号：US18168392

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Pi CHANG ,  Chung-Liang CHENG ,  I-Ming CHANG ,  Yao-Sheng HUANG ,  Huang-Lin CHAO

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/8234 ,  H01L29/40

CPC classification number: H01L29/513 ,  H01L29/7851 ,  H01L21/3115 ,  H01L21/823462 ,  H01L29/401

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming an interfacial oxide layer on the fin structure, forming a first dielectric layer over the interfacial oxide layer, forming a dipole layer between the interfacial oxide layer and the first dielectric layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The dipole layer includes ions of first and second metals that are different from each other. The first and second metals have electronegativity values greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer.