公开(公告)号：US11417750B2

公开(公告)日：2022-08-16

申请号：US17122721

申请日：2020-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Ning Yao ,  Bo-Feng Young ,  Sai-Hooi Yeong ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/49 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

Abstract: Fin-like field effect transistors (FinFETs) and methods of fabrication thereof are disclosed herein. The FinFETs disclosed herein have gate air spacers integrated into their gate structures. An exemplary transistor includes a fin and a gate structure disposed over the fin between a first epitaxial source/drain feature and a second epitaxial source/drain feature. The gate structure includes a gate electrode, a gate dielectric, and gate air spacers disposed between the gate dielectric and sidewalls of the gate electrode.

公开(公告)号：US20220173252A1

公开(公告)日：2022-06-02

申请号：US17674361

申请日：2022-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3115 ,  H01L29/786

Abstract: A semiconductor device and method of manufacture are provided which utilizes metallic seeds to help crystallize a ferroelectric layer. In an embodiment a metal layer and a ferroelectric layer are formed adjacent to each other and then the metal layer is diffused into the ferroelectric layer. Once in place, a crystallization process is performed which utilizes the material of the metal layer as seed crystals.

公开(公告)号：US20220123003A1

公开(公告)日：2022-04-21

申请号：US17076505

申请日：2020-10-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui ,  Chun-Chieh Lu ,  Yu-Ming Lin

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  G11C7/18 ,  G11C8/14

Abstract: In an embodiment, a method includes forming a multi-layer stack including alternating layers of an isolation material and a semiconductor material, patterning the multi-layer stack to form a first channel structure in a first region of the multi-layer stack, where the first channel structure includes the semiconductor material, depositing a memory film layer over the first channel structure, etching a first trench extending through a second region of the multi-layer stack to form a first dummy bit line and a first dummy source line in the second region, where the first dummy bit line and first dummy source line each include the semiconductor material, and replacing the semiconductor material of the first dummy bit line and the first dummy source line with a conductive material to form a first bit line and a first source line.

公开(公告)号：US20210376153A1

公开(公告)日：2021-12-02

申请号：US17072367

申请日：2020-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chih-Yu Chang

IPC: H01L29/78 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/786 ,  H01L29/04 ,  H01L29/66 ,  H01L29/24

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor comprising: a ferroelectric (FE) material contacting a word line, the FE material being a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line.

公开(公告)号：US20210265366A1

公开(公告)日：2021-08-26

申请号：US16798719

申请日：2020-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Chung-Te Lin ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Sheng-Chih Lai ,  Chih-Yu Chang ,  Han-Jong Chia

IPC: H01L27/1159 ,  H01L27/12 ,  G11C11/22

Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a substrate. A gate dielectric is disposed over the substrate and between the source/drain regions. A gate electrode is disposed on the gate dielectric. A polarization switching structure is disposed on the gate electrode. A pair of sidewall spacers is disposed over the substrate and along opposite sidewalls of the gate electrode and the polarization switching structure.

公开(公告)号：US20210234017A1

公开(公告)日：2021-07-29

申请号：US17107374

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Ning Yao ,  Bo-Feng Young ,  Sai-Hooi Yeong ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/764 ,  H01L29/66

Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate stack having a top portion disposed over the stack of semiconductor layers and a bottom portion interleaved with the stack of semiconductor layers, an inner spacer disposed on sidewalls of the bottom portion of the metal gate stack, an air gap enclosed in the inner spacer, and an epitaxial source/drain (S/D) feature disposed over the inner spacer and adjacent to the metal gate stack.

公开(公告)号：US10861968B1

公开(公告)日：2020-12-08

申请号：US16427078

申请日：2019-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Chih-Yu Chang ,  Sai-Hooi Yeong ,  Chi-On Chui ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/51 ,  H01L29/24 ,  H01L29/66 ,  H01L29/40 ,  H01L21/467

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a fin structure that includes a negative capacitance (NC) material. The semiconductor device structure also includes a gate electrode layer, a gate dielectric structure, a source feature, and a drain feature. The gate dielectric structure covers the top surface and the opposing sidewall surfaces of the fin structure. The gate electrode layer is formed over the gate dielectric structure. The source feature and the drain feature are formed in and protrude from the fin structure, and separated from each other by the gate electrode layer.

公开(公告)号：US20170077302A1

公开(公告)日：2017-03-16

申请号：US14854772

申请日：2015-09-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Wen Cheng ,  Che-Cheng Chang ,  Mu-Tsang Lin ,  Bo-Feng Young ,  Cheng-Yen Yu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

Abstract: The present disclosure relates to a semiconductor device that controls a strain on a channel region by forming a dielectric material in recesses, adjacent to a channel region, in order to provide control over a volume and shape of a strain inducing material of epitaxial source/drain regions formed within the recesses. In some embodiments, the semiconductor device has epitaxial source/drain regions arranged in recesses within an upper surface of a semiconductor body on opposing sides of a channel region. A gate structure is arranged over the channel region, and a dielectric material is arranged laterally between the epitaxial source/drain regions and the channel region. The dielectric material consumes some volume of the recesses, thereby reducing a volume of strain inducing material in epitaxial source/drain regions formed in the recesses.

Abstract translation: 本公开涉及一种半导体器件，其通过在与沟道区相邻的凹槽中形成介电材料来控制沟道区上的应变，以便提供对外延源极/漏极的应变诱导材料的体积和形状的控制 形成在凹部内的区域。 在一些实施例中，半导体器件具有布置在沟道区域的相对侧上的半导体本体的上表面内的凹槽中的外延源极/漏极区域。 栅极结构布置在沟道区域上方，并且电介质材料横向布置在外延源极/漏极区域和沟道区域之间。 电介质材料消耗一些体积的凹槽，从而减少在凹陷中形成的外延源极/漏极区域中的应变诱发材料的体积。

公开(公告)号：US12302553B2

公开(公告)日：2025-05-13

申请号：US17668770

申请日：2022-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Bo-Feng Young ,  Hung Wei Li ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H10B12/00 ,  H01L29/10

Abstract: Embodiments of the present disclosure provide a side-channel dynamic random access memory (DRAM) cell and cell array that utilizes a vertical design with side channel transistors. A dielectric layer disposed over a substrate. A gate electrode is embedded in the dielectric layer. A channel layer wraps the gate electrode and a conductive structure is adjacent to the channel layer, with the channel layer interposed between the gate electrode and the conductive structure. The semiconductor structure also includes a dielectric structure disposed over the conductive structure and the gate electrode, the channel layer extending up through the dielectric structure.

公开(公告)号：US12256550B2

公开(公告)日：2025-03-18

申请号：US18327439

申请日：2023-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Meng-Han Lin ,  Chih-Yu Chang ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: H10B51/20 ,  H01L21/02 ,  H01L23/522 ,  H01L29/24 ,  H10B51/30

Abstract: A memory cell includes patterning a first trench extending through a first conductive line, depositing a memory film along sidewalls and a bottom surface of the first trench, depositing a channel layer over the memory film, the channel layer extending along the sidewalls and the bottom surface of the first trench, depositing a first dielectric layer over and contacting the channel layer to fill the first trench, patterning a first opening, wherein patterning the first opening comprises etching the first dielectric layer, depositing a gate dielectric layer in the first opening, and depositing a gate electrode over the gate dielectric layer and in the first opening, the gate electrode being surrounded by the gate dielectric layer.