公开(公告)号：US20230253480A1

公开(公告)日：2023-08-10

申请号：US18301704

申请日：2023-04-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/768

CPC classification number: H01L29/6656 ,  H01L29/785 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/6681 ,  H01L21/823437 ,  H01L29/66545 ,  H01L21/7682

Abstract: A method includes forming a dummy gate over a substrate. A first gate spacer is formed on a sidewall of the dummy gate. The dummy gate is replaced with a gate structure. A top portion of the first spacer is removed. After the top portion of the first spacer is removed, a second spacer is over the first spacer. The second spacer has a stepped bottom surface with an upper step in contact with a top surface of the first spacer and a lower step lower than the top surface of the first spacer. A contact plug is formed contacting the gate structure and the second spacer.

公开(公告)号：US20220344464A1

公开(公告)日：2022-10-27

申请号：US17238983

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chuang CHIU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Chih-Hao WANG ,  Huan-Chieh SU ,  Chun-Yuan CHEN ,  Li-Zhen YU ,  Yu-Ming LIN

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

公开(公告)号：US20210398845A1

公开(公告)日：2021-12-23

申请号：US17464012

申请日：2021-09-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Wai-Yi LIEN ,  Yu-Ming LIN

IPC: H01L21/768 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/28 ,  H01L23/485 ,  H01L29/417

Abstract: A device includes a substrate, a first metal feature over the substrate, first and second spacers, a first dielectric layer, and a second metal feature. The first and second spacers are on opposite sidewalls of the conductive feature, respectively. The first dielectric layer is in contact with the first spacer, in which a top surface of the protection layer is higher than a top surface of the first spacer. The second metal feature is electrically connected to the first metal structure and in contact with a top surface and a sidewall of the protection layer.

公开(公告)号：US20210249537A1

公开(公告)日：2021-08-12

申请号：US16785985

申请日：2020-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao CHANG ,  Sheng-Tsung WANG ,  Lin-Yu HUANG ,  Chia-Lin CHUANG ,  Cheng-Chi CHUANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L21/764 ,  H01L29/08

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure includes a gate stack wrapping around a first upper portion of the fin. The semiconductor device structure includes a first stressor and a second stressor respectively over opposite first sides of the fin. The semiconductor device structure includes a spacer structure between the gate stack and the first stressor. The semiconductor device structure includes a first spacer layer covering a sidewall of the gate stack, the spacer structure, and the first stressor. The semiconductor device structure includes a dielectric layer over the first spacer layer. The semiconductor device structure includes an etch stop layer between the first spacer layer and the dielectric layer. The semiconductor device structure includes a seal structure between the second upper portion and the third upper portion.

公开(公告)号：US20210202744A1

公开(公告)日：2021-07-01

申请号：US17201812

申请日：2021-03-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/28 ,  H01L21/321 ,  H01L21/768 ,  H01L29/417

Abstract: A method comprises forming a gate structure over a substrate; forming a gate helmet to cap the gate structure; forming a source/drain contact on the substrate; depositing a contact etch stop layer (CESL) over the gate helmet and the source/drain contacts, and an interlayer dielectric (ILD) layer over the CESL; performing a first etching process to form a gate contact opening extending through the ILD layer, the CESL and the gate helmet to the gate structure; forming a metal cap in the gate contact opening; with the metal cap in the gate contact opening, performing a second etching process to form a source/drain via opening extending through the ILD layer, the CESL to the source/drain contact; and after forming the source/drain via opening, forming a gate contact over the metal cap and a source/drain via over the source/drain contact.

公开(公告)号：US20210057569A1

公开(公告)日：2021-02-25

申请号：US16548423

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu HUANG ,  Jia-Chuan YOU ,  Chia-Hao CHANG ,  Tien-Lu LIN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/308

Abstract: A method for forming a semiconductor device structure is provided. The method for forming the semiconductor device structure includes forming a first mask layer covering the gate stack, forming a contact alongside the gate stack and the first mask layer, recessing the contact, etching the first mask layer, and forming a second mask layer covering the contact and a portion of the first mask layer.

公开(公告)号：US20200381299A1

公开(公告)日：2020-12-03

申请号：US16999997

申请日：2020-08-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Wei-Hao WU ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L23/522 ,  H01L21/033

Abstract: A semiconductor device includes a substrate, a gate stack, a first gate spacer and a second gate spacer, a first source/drain region and a second source/drain region, a first conductive feature and a second conductive feature, and a first contact plug and a second contact plug. The first conductive feature and the second conductive feature are over the first source/drain region and the second source/drain region, respectively. The first conductive cap and the second conductive cap are over the first conductive feature and the second conductive feature, respectively. The first contact plug and the second contact plug are over the first conductive cap and the second conductive cap, respectively, in which the first contact plug is separated from the first gate spacer, and the second contact plug is in contact with a sidewall and a top surface of the second gate spacer.

公开(公告)号：US20200350422A1

公开(公告)日：2020-11-05

申请号：US16933100

申请日：2020-07-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hao WANG ,  Wai-Yi LIEN ,  Gwan-Sin CHANG ,  Yu-Ming LIN ,  Ching HSUEH ,  Jia-Chuan YOU ,  Chia-Hao CHANG

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor fin on a substrate. A dummy gate structure is formed crossing the semiconductor fin. The dummy gate structure is replaced with a metal gate structure. An epitaxial structure is formed in the semiconductor fin after replacing the dummy gate structure with the metal gate structure.

公开(公告)号：US20190019882A1

公开(公告)日：2019-01-17

申请号：US16128479

申请日：2018-09-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Ming LIN ,  Ken-Ichi GOTO

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L23/535 ,  H01L29/10 ,  H01L29/16 ,  H01L29/24 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02521 ,  H01L21/02527 ,  H01L21/02568 ,  H01L21/0262 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/1037 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device including a Fin FET device includes a fin structure protruding from a substrate layer and having a length extending in a first direction. A channel layer is formed on the fin structure. A gate stack including a gate electrode layer and a gate dielectric layer extending in a second direction perpendicular to the first direction is formed over the channel layer covering a portion of the length of the fin structure. The source and drain contacts are formed over trenches that extend into a portion of a height of the fin structure.

公开(公告)号：US20180366666A1

公开(公告)日：2018-12-20

申请号：US15627722

申请日：2017-06-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh LU ,  Jean-Pierre COLINGE ,  Ken-Ichi GOTO ,  Zhiqiang WU ,  Yu-Ming LIN

IPC: H01L51/05 ,  H01L51/00 ,  H01L51/10

CPC classification number: H01L51/057 ,  H01L51/0003 ,  H01L51/0048 ,  H01L51/0525 ,  H01L51/055 ,  H01L51/0558 ,  H01L51/105

Abstract: In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.