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    NOVEL RESISTIVE RANDOM ACCESS MEMORY DEVICE
    21.
    发明申请
    NOVEL RESISTIVE RANDOM ACCESS MEMORY DEVICE 审中-公开

    公开(公告)号：US20200027506A1

    公开(公告)日：2020-01-23

    申请号：US16588383

    申请日：2019-09-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Fu LEE ,  Yu-Der CHIH

    IPC: G11C13/00

    Abstract: A memory device includes: a memory bit cell; a write circuit, coupled to the memory bit cell, and configured to use a first voltage to transition the memory bit cell to a first logic state by changing a respective resistance state of the memory bit cell, and compare a first current flowing through the memory bit cell with a first reference current; and a control logic circuit, coupled to the write circuit, and configured to determine whether the first logic state is successfully written into the memory bit cell based on a read-out logic state of the memory bit cell and the comparison between the first current and first reference current.

    NOVEL MEMORY DEVICE
    22.
    发明申请
    NOVEL MEMORY DEVICE 审中-公开

    公开(公告)号：US20190163568A1

    公开(公告)日：2019-05-30

    申请号：US15965883

    申请日：2018-04-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chien-Yin LIU ,  Yu-Der CHIH ,  Hsueh-Chu YANG ,  Jonathan Tehan CHEN ,  Kuan-Chun CHEN

    IPC: G06F11/10 ,  G11C16/26 ,  G11C11/56 ,  G11C29/42 ,  G11C29/52

    Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N−1 groups and the plurality of parity bits form a first group different from the N−1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N−1 groups; and providing a second word comprising updated data bits that form a second one of the N−1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N−1 groups.

    MEMORY DEVICE AND REFERENCE CIRCUIT THEREOF
    23.
    发明申请
    MEMORY DEVICE AND REFERENCE CIRCUIT THEREOF 有权

    公开(公告)号：US20220115051A1

    公开(公告)日：2022-04-14

    申请号：US17559998

    申请日：2021-12-22

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chia-Fu LEE ,  Yu-Der CHIH ,  Hon-Jarn LIN ,  Yi-Chun SHIH

    IPC: G11C11/16 ,  G11C7/06 ,  G11C7/22 ,  G11C13/00

    Abstract: A device includes first and second reference storage units, and first and second reference switches. The first reference switch outputs a first current at a first terminal thereof to the first reference storage unit. The first reference storage unit receives the first current at a first terminal thereof and generates a first signal, according to the first current, at a second terminal thereof to an average current circuit. The second reference switch outputs a second current at a first terminal thereof to the second reference storage unit. The second reference storage unit receives the second current at a first terminal thereof, and generates a second signal, according to the second current, at a second terminal thereof to the average current circuit. The first and second reference switches are coupled to a plurality of first memory cells by a first word line.

    LOW-DROPOUT REGULATOR CIRCUIT
    24.
    发明申请
    LOW-DROPOUT REGULATOR CIRCUIT 有权

    公开(公告)号：US20210294368A1

    公开(公告)日：2021-09-23

    申请号：US17339818

    申请日：2021-06-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-An CHANG ,  Chia-Fu LEE ,  Yu-Der CHIH ,  Yi-Chun SHIH

    IPC: G05F1/56

    Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.

    RESISTIVE RANDOM ACCESS MEMORY DEVICE
    25.
    发明申请
    RESISTIVE RANDOM ACCESS MEMORY DEVICE 有权

    公开(公告)号：US20210280245A1

    公开(公告)日：2021-09-09

    申请号：US17330248

    申请日：2021-05-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Der CHIH ,  Chung-Cheng CHOU ,  Wen-Ting CHU

    IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

    Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.

    NOVEL MEMORY DEVICE
    26.
    发明申请
    NOVEL MEMORY DEVICE 有权

    公开(公告)号：US20210224154A1

    公开(公告)日：2021-07-22

    申请号：US17222919

    申请日：2021-04-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chien-Yin LIU ,  Yu-Der CHIH ,  Hsueh-Chih YANG ,  Jonathan Tehan CHEN ,  Kuan-Chun CHEN

    IPC: G06F11/10 ,  G11C16/26 ,  G11C29/42 ,  G11C29/52

    Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N−1 groups and the plurality of parity bits form a first group different from the N−1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N−1 groups; and providing a second word comprising updated data bits that form a second one of the N−1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N−1 groups.

    LOW-DROPOUT REGULATOR CIRCUIT
    27.
    发明申请
    LOW-DROPOUT REGULATOR CIRCUIT 审中-公开

    公开(公告)号：US20200150703A1

    公开(公告)日：2020-05-14

    申请号：US16738963

    申请日：2020-01-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-An CHANG ,  Chia-Fu LEE ,  Yu-Der CHIH ,  Yi-Chun SHIH

    IPC: G05F1/56

    Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.

    NOVEL MEMORY DEVICE
    29.
    发明申请
    NOVEL MEMORY DEVICE 审中-公开

    公开(公告)号：US20190221276A1

    公开(公告)日：2019-07-18

    申请号：US16159214

    申请日：2018-10-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Der CHIH ,  Chien-Yin LIU ,  Yi-Chun SHIH

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

    CPC classification number: G11C16/3459 ,  G11C16/10 ,  G11C16/26

    Abstract: A circuit includes: writing a plurality of data words, each of which has a plurality of data bits, into respective bit cells of a memory device; in response to determining that not all the data bits of the plurality of data words are correctly written into the respective bit cells of the memory device, grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that were not correctly written into the respective bit cells of the memory device, wherein the subset of the data bits are contained in a respective one of the plurality of data word sets.

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