公开(公告)号：US20200302998A1

公开(公告)日：2020-09-24

申请号：US16895069

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuhsiang CHEN ,  Shao-Yu CHOU ,  Chun-Hao CHANG ,  Min-Shin WU ,  Yu-Der CHIH

IPC: G11C11/419 ,  G11C11/418

Abstract: Memories are provided. A memory includes a first memory array, a second memory array, and a read circuit. The first memory array is configured to store main data. The second memory array is configured to store complement data that is complementary to the main data. The read circuit includes a first sense amplifier, a second sense amplifier and an output buffer. The first sense amplifier is configured to provide a first sensing signal according to a reference signal and first data of the main data corresponding to a first address signal. The second sense amplifier is configured to provide a second sensing signal according to the reference signal and second data of the complement data corresponding to the first address signal. The output buffer is configured to provide one of the first sensing signal and the second sensing signal as an output according to a control signal.

公开(公告)号：US20190097420A1

公开(公告)日：2019-03-28

申请号：US16143315

申请日：2018-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hung CHEN ,  Kuo-Ji CHEN ,  Shao-Yu CHOU

IPC: H02H9/04 ,  H01L27/02 ,  H03K17/082

Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the second voltage is higher than the ground voltage; and a voltage divider circuit operatively coupled to the first bus at the first voltage and the second bus at the ground voltage, wherein the voltage divider circuit is operatively coupled to the first single-gate-oxide ESD control circuit and the second single-gate-oxide ESD control circuit at the first node.

公开(公告)号：US20140073124A1

公开(公告)日：2014-03-13

申请号：US14079671

申请日：2013-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Huei CHEN ,  Jung-Hsuan CHEN ,  Shao-Yu CHOU ,  Hung-Jen LIAO ,  Li-Chun TIEN

IPC: H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/28123 ,  H01L21/823425 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/66628 ,  H01L29/7848

Abstract: A method includes forming a first plurality of fingers over an active area of a semiconductor substrate. Each of the first plurality of fingers has a respective length that extends in a direction that is parallel to width direction of the active area. The first plurality of fingers form at least one gate of at least one transistor having a source and a drain formed by a portion of the active area. A first dummy polysilicon structure is formed over a portion of the active area between an outer one of the first plurality of fingers and a first edge of the semiconductor substrate. A second dummy polysilicon structure is over the semiconductor substrate between the first dummy polysilicon structure and the first edge of the semiconductor substrate.

Abstract translation: 一种方法包括在半导体衬底的有效区域上形成第一多个指状物。 第一多个指状物中的每一个具有在与有源区域的宽度方向平行的方向上延伸的相应长度。 第一多个指状物形成至少一个晶体管的至少一个栅极，该晶体管具有由有源区域的一部分形成的源极和漏极。 第一虚设多晶硅结构形成在第一多个指状物的外部之一和半导体衬底的第一边缘之间的有源区域的一部分上。 第二虚设多晶硅结构在第一虚设多晶硅结构和半导体衬底的第一边缘之间的半导体衬底之上。

公开(公告)号：US20190244660A1

公开(公告)日：2019-08-08

申请号：US16390517

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuhsiang CHEN ,  Shao-Yu CHOU ,  Chun-Hao CHANG ,  Min-Shin WU ,  Yu-Der CHIH

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/1012 ,  G11C7/1051 ,  G11C11/409 ,  G11C11/413 ,  G11C11/418

Abstract: Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes an output buffer. The output buffer is configured to simultaneously obtain first data from the first memory array and second data from the second memory array according a first address signal, and selectively provide the first data or the second data as an output according to a control signal. Binary representation of the first data is complementary to that of the second data.

公开(公告)号：US20180166131A1

公开(公告)日：2018-06-14

申请号：US15619084

申请日：2017-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yuhsiang CHEN ,  Shao-Yu CHOU ,  Chun-Hao CHANG ,  Min-Shin WU ,  Yu-Der CHIH

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/1012 ,  G11C7/1051 ,  G11C11/409 ,  G11C11/413 ,  G11C11/418

Abstract: Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes a first decoder coupled to the first memory array, a second decoder coupled to the second memory array, and an output buffer. The first decoder obtains first data from the first memory array according a first address signal. The second decoder obtains second data from the second memory array according the first address signal. The output buffer selectively provides the first data or the second data as an output according to a control signal. The first data is complementary to the second data.

公开(公告)号：US20150118803A1

公开(公告)日：2015-04-30

申请号：US14589009

申请日：2015-01-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsien-Yu PAN ,  Jung-Hsuan CHEN ,  Shao-Yu CHOU ,  Yen-Huei CHEN ,  Hung-Jen LIAO

IPC: H01L27/11 ,  H01L21/768 ,  H01L27/02

CPC classification number: H01L27/1116 ,  H01L21/768 ,  H01L27/0207 ,  H01L27/11 ,  H01L2027/11887

Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.

Abstract translation: 用于形成字线解码器装置和具有字线解码器单元的其它装置的方法和布局提供了使用非DPL光刻操作形成金属互连层，并且使用下部或中间金属层或下部导电材料提供了用于缝合的远端布置的晶体管。 晶体管可以设置在纵向布置的字线解码器或其他单元中或其附近，并且使用金属或导电材料的导电耦合降低晶体管之间的栅极电阻并避免RC信号延迟。