公开(公告)号：US11437084B2

公开(公告)日：2022-09-06

申请号：US17177627

申请日：2021-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yong-Shiuan Tsair

IPC: H01L21/00 ,  G11C11/22 ,  H01L27/11592 ,  H01L27/1159 ,  H01L29/51

Abstract: The present disclosure relates to a method of forming a memory structure. The method includes depositing a ferroelectric random access memory (FeRAM) stack over a substrate. The FeRAM stack has a ferroelectric layer and one or more conductive layers over the ferroelectric layer. The FeRAM stack is patterned to define an FeRAM device stack. A sidewall spacer is formed along a first side of the FeRAM device stack, and a select gate is formed along a side of the sidewall spacer that faces away from the FeRAM device stack. A source region is formed within the substrate and along a second side of the FeRAM device stack, and a drain region is formed within the substrate. The drain region is separated from the FeRAM device stack by the select gate.

公开(公告)号：US11296116B2

公开(公告)日：2022-04-05

申请号：US16727673

申请日：2019-12-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fu-Chen Chang ,  Kuo-Chi Tu ,  Tzu-Yu Chen ,  Sheng-Hung Shih

IPC: H01L27/11 ,  H01L27/1159 ,  H01L27/11587 ,  G11C11/22 ,  H01L49/02 ,  H01L27/11507 ,  H01L27/11502

Abstract: A semiconductor device includes an inter-metal dielectric layer, a first conductive line, and a first ferroelectric random access memory (FRAM) structure. The first conductive line is embedded in the inter-metal dielectric layer and extends along a first direction. The first FRAM structure is over inter-metal dielectric layer and includes a bottom electrode layer, a ferroelectric layer, and a top electrode layer. The bottom electrode layer is over the first conductive line and has an U-shaped when viewed in a cross section taken along a second direction substantially perpendicular to the first direction. The ferroelectric layer is conformally formed on the bottom electrode. The top electrode layer is over the ferroelectric layer.

公开(公告)号：US11227872B2

公开(公告)日：2022-01-18

申请号：US16394207

申请日：2019-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Chang ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Tzu-Yu Chen ,  Fu-Chen Chang

IPC: H01L27/11585 ,  G11C11/22 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28

Abstract: In some embodiments, the present disclosure relates to an integrated chip including one or more lower interconnect layers arranged within one or more stacked inter-layer dielectric layers over a substrate. A bottom electrode is disposed over the one or more interconnect layers, and a top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts a first surface of the bottom electrode and a second surface of the top electrode. The ferroelectric layer includes a protrusion that extends past outer surfaces of the top electrode and the bottom electrode along a first direction that is perpendicular to a second direction that is normal to the first surface. The protrusion is confined between lines that extend along the first and second surface.

公开(公告)号：US11195840B2

公开(公告)日：2021-12-07

申请号：US16452965

申请日：2019-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Yong-Shiuan Tsair

IPC: H01L27/11507 ,  H01L49/02

Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.

公开(公告)号：US11183503B2

公开(公告)日：2021-11-23

申请号：US16663952

申请日：2019-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Chih-Hsiang Chang ,  Fu-Chen Chang

IPC: H01L27/11502 ,  H01L27/11507 ,  H01L49/02 ,  G11C11/22 ,  H01L27/11504

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure.

公开(公告)号：US20190333920A1

公开(公告)日：2019-10-31

申请号：US15964702

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yong-Shiuan Tsair

IPC: H01L27/11507 ,  H01L29/06 ,  H01L27/11509 ,  H01L21/311 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78

Abstract: Various embodiments of the present application are directed to a method for forming a boundary structure separating a memory cell and a logic device. In some embodiments, an isolation structure is formed separating a memory semiconductor region from a logic semiconductor region. A memory cell structure is formed on the memory semiconductor region, and a memory capping layer is formed covering the memory cell structure and the logic semiconductor region. A first etch is performed into the memory capping layer to remove the memory capping layer from the logic semiconductor region, and to define a slanted, logic-facing sidewall on the isolation structure. A logic device structure is formed on the logic semiconductor region. Further, a second etch is performed into the memory capping layer to remove the memory capping layer from the memory semiconductor, while leaving a dummy segment of the memory capping layer that defines the logic-facing sidewall.

公开(公告)号：US09831262B2

公开(公告)日：2017-11-28

申请号：US14984095

申请日：2015-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Tzu-Yu Chen

IPC: H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L27/11582 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/6656 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a high-k metal gate (HKMG) non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a memory region having a select transistor and a control transistor laterally spaced apart over a substrate. A select gate electrode and a control gate electrode are disposed over a high-k gate dielectric layer and a memory gate oxide. A logic region is disposed adjacent to the memory region and has a logic device including a metal gate electrode disposed over the high-k gate dielectric layer and a logic gate oxide. The select gate electrode and the control gate electrode can be polysilicon electrodes.