Test Circuit And Method
    22.
    发明申请
    Test Circuit And Method 有权
    测试电路和方法

    公开(公告)号:US20150241507A1

    公开(公告)日:2015-08-27

    申请号:US14189112

    申请日:2014-02-25

    CPC分类号: G01R31/265 G01R31/3025

    摘要: A method is disclosed that includes the operations outlined below. For a plurality of dies on a test fixture, an antenna distance between each of first antennas of one of the dies and every one of first antennas of the other dies is determined. The dies are categorized into die groups, wherein the antenna distance between each of the first antennas of one of the dies in one of the die groups and every one of the first antennas of the other dies in the same one of the die groups is larger than an interference threshold. Test processes are sequentially performed on the die groups. Each of the test processes is performed according to signal transmissions between the first antennas and second antennas of the under-test device each positionally corresponds to one of the first antennas.

    摘要翻译: 公开了一种包括以下概述的操作的方法。 对于测试夹具上的多个管芯,确定一个管芯的每个第一天线与另一个管芯的每个第一天线之间的天线距离。 模具被分类为管芯组,其中一个管芯组中的一个管芯中的一个管芯的每个第一个天线之间的天线距离和另一个管芯组中的另一个管芯的每个第一个天线之间的天线距离较大 比干扰阈值。 在模具组上依次执行测试过程。 每个测试过程根据第一天线与被测设备的第二天线之间的信号传输进行,每个位置上对应于第一天线之一。

    Semiconductor package having channels formed between through-insulator-vias

    公开(公告)号:US11322453B2

    公开(公告)日:2022-05-03

    申请号:US16697133

    申请日:2019-11-26

    发明人: Sen-Kuei Hsu

    摘要: A semiconductor package includes a die, through insulator vias, an encapsulant, and a pair of metallization layers. The through insulator vias are disposed beside the die. The encapsulant wraps the die and the through insulator vias. The pair of metallization layers is disposed on opposite sides of the encapsulant. One end of each through insulator via contacts one of the metallization layers and the other end of each through insulator via contacts the other metallization layer. The through insulator vias form at least one photonic crystal structure. A pair of the through insulator vias is separated along a first direction by a channel filled by the encapsulant. A width of the channel along the first direction is larger than a pitch of the photonic crystal structure along the first direction.

    Test circuit and method
    25.
    发明授权

    公开(公告)号:US10725090B2

    公开(公告)日:2020-07-28

    申请号:US15893466

    申请日:2018-02-09

    IPC分类号: G01R31/265 G01R31/302

    摘要: A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.

    Semiconductor package
    27.
    发明授权

    公开(公告)号:US11508666B2

    公开(公告)日:2022-11-22

    申请号:US16914480

    申请日:2020-06-29

    摘要: A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.

    SEMICONDUCTOR PACKAGE
    28.
    发明申请

    公开(公告)号:US20210407914A1

    公开(公告)日:2021-12-30

    申请号:US16914480

    申请日:2020-06-29

    摘要: A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.