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公开(公告)号：US11340291B2
公开(公告)日：2022-05-24
申请号：US16912017
申请日：2020-06-25
发明人： Mill-Jer Wang , Kuo-Chuan Liu , Ching-Nen Peng , Hung-Chih Lin , Hao Chen
IPC分类号： G01R31/28 , G01R31/3185 , G01R1/04 , G01R1/067
摘要： A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.
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公开(公告)号：US20210063471A1
公开(公告)日：2021-03-04
申请号：US16805874
申请日：2020-03-02
发明人： Hao Chen , Mill-Jer Wang
摘要： A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.
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公开(公告)号：US09417285B2
公开(公告)日：2016-08-16
申请号：US14141529
申请日：2013-12-27
发明人： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen
IPC分类号： G01R31/3185 , G01R1/04 , G01R31/28
CPC分类号： G01R31/318513 , G01R1/0466 , G01R31/2886 , H01L2924/15192
摘要： A device for testing a bottom package of an integrated fan-out (InFO) Package-on-Package (PoP) comprises a bottom fixture having a space to accommodate the bottom package during testing and a detachable top cover, configured for conducting at least one test of the bottom package, wherein one or both of the bottom fixture and the top cover have a plurality of probing contacts for testing of the bottom package and wherein the device can be opened for placement of the bottom package under testing, and the cover is attachable to the bottom fixture for conducting the testing.
摘要翻译： 用于测试集成扇出（InFO）封装封装（PoP）的底部封装的装置包括底部夹具，其具有在测试期间容纳底部封装的空间和可拆卸的顶盖，其被配置用于进行至少一个 底部包装的测试，其中底部固定装置和顶盖中的一个或两个具有多个用于测试底部包装的探测触点，并且其中该装置可以被打开以放置待测试的底部包装，并且盖是 可附接到底部夹具进行测试。
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公开(公告)号：US09372227B2
公开(公告)日：2016-06-21
申请号：US13792323
申请日：2013-03-11
发明人： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Wei-Hsun Lin , Hao Chen , Chung-Han Huang
CPC分类号： G01R31/2889 , G01R31/2884
摘要： A system for testing a device under test (DUT) includes a probe card and a test module. The probe card includes probe beds electrically coupled to a circuit board and a first plurality of electrical contacts coupled to the circuit board, which are for engaging respective ones of a plurality of electrical contacts of a test equipment module. Probes are coupled to respective probe beds and are disposed to engage electrical contacts of the DUT. The probe card includes a second plurality of electrical contacts coupled to the circuit board. The first and second pluralities of contacts are mutually exclusive. The test module includes a memory, a processor, and a plurality of electrical contacts electrically coupled to respective ones of the second plurality of electrical contacts of the probe card. The circuit board includes a first electrical path for electrically coupling the test equipment module to the test module.
摘要翻译： 用于测试被测器件（DUT）的系统包括探针卡和测试模块。 探针卡包括电耦合到电路板的探针台和耦合到电路板的第一多个电触点，其用于接合测试设备模块的多个电触点中的相应的一个。 探针耦合到相应的探针台并且被设置成接合DUT的电触点。 探针卡包括耦合到电路板的第二多个电触点。 第一和第二个联系人是相互排斥的。 测试模块包括存储器，处理器和电耦合到探针卡的第二多个电触点中的相应电触头的多个电触头。 电路板包括用于将测试设备模块电耦合到测试模块的第一电路径。
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5.发明授权公开(公告)号：US09252593B2
公开(公告)日：2016-02-02
申请号：US13716272
申请日：2012-12-17
发明人： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen
CPC分类号： H05F3/02 , G01R1/07378 , G01R1/36 , H01L2924/15174 , H01L2924/15311 , H02H9/046 , H05K1/11 , H05K1/181 , H05K2201/07 , H05K2201/10734
摘要： The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.
摘要翻译： 本公开提供了一种用于提供静电放电保护的系统和方法。 提供一种电连接到多个输入/输出通道的探针卡组件。 探针卡组件可以与具有电连接到一个或多个晶片的插入器的次级组件接触，每个晶片具有被测器件。 可以将电压强制在探针卡组件的多个输入/输出通道中的一个上，以缓慢地耗散驻留在晶片上的电荷，从而提供静电放电保护。 还提供了适于接受3DIC封装的插座组件，该组件具有电连接到多个输入/输出通道的装载板组件。 一旦将3DIC封装放置在插座组件中，则强制在输入/输出通道之间施加电压以缓慢耗散驻留在3DIC封装上的电荷，从而提供静电放电保护。
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公开(公告)号：US20150168459A1
公开(公告)日：2015-06-18
申请号：US14132722
申请日：2013-12-18
发明人： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen , Chung-Han Huang
CPC分类号： G01R27/2605 , G01R31/2856
摘要： A circuit that includes a stacked circuit layer, a plurality of test contact points and a comparator is disclosed. The stacked circuit layer includes a plurality of reference capacitors each having a reference capacitance. Each of the test contact points is electrically connecting to an under-test capacitor of an under-test module. The comparator compares the reference capacitance of one of the reference capacitors with an under-test capacitance of the under-test capacitor corresponding to one of the test contact points to measure a range of the under-test capacitance.
摘要翻译： 公开了一种包括堆叠电路层，多个测试接触点和比较器的电路。 叠层电路层包括各自具有参考电容的多个参考电容器。 每个测试接触点电连接到被测试模块的测试不足的电容器。 比较器将参考电容器之一的参考电容与对应于一个测试接点的欠压电容器的受测电容进行比较，以测量未测试电容的范围。
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公开(公告)号：US09891266B2
公开(公告)日：2018-02-13
申请号：US14189112
申请日：2014-02-25
发明人： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Sen-Kuei Hsu , Chuan-Ching Wang , Hao Chen
IPC分类号： G01R31/265 , G01R31/302
CPC分类号： G01R31/265 , G01R31/3025
摘要： A method is disclosed that includes the operations outlined below. For a plurality of dies on a test fixture, an antenna distance between each of first antennas of one of the dies and every one of first antennas of the other dies is determined. The dies are categorized into die groups, wherein the antenna distance between each of the first antennas of one of the dies in one of the die groups and every one of the first antennas of the other dies in the same one of the die groups is larger than an interference threshold. Test processes are sequentially performed on the die groups. Each of the test processes is performed according to signal transmissions between the first antennas and second antennas of the under-test device each positionally corresponds to one of the first antennas.
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公开(公告)号：US09640447B2
公开(公告)日：2017-05-02
申请号：US14186107
申请日：2014-02-21
发明人： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen , Chung-Han Huang
CPC分类号： H01L22/14 , G01R31/2889
摘要： A circuit is disclosed that includes a signal-forcing path, a discharging path, a contact probe, a monitoring probe and a switch module. The signal-forcing path is connected to a signal source. The discharging path is connected to a discharging voltage terminal. The contact probe contacts a pad module of an under-test device. The monitoring probe generates a monitored voltage associated with the pad module. The switch module is operated in a discharging mode to connect the contact probe to the discharging path when the monitored voltage does not reach a threshold voltage such that the under-test device is discharged and is operated in an operation mode to connect the contact probe to the signal-forcing path when the monitored voltage reaches the threshold voltage such that a signal generated by the signal source is forced to the under-test device.
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公开(公告)号：US09606155B2
公开(公告)日：2017-03-28
申请号：US14132722
申请日：2013-12-18
发明人： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen , Chung-Han Huang
CPC分类号： G01R27/2605 , G01R31/2856
摘要： A circuit includes a stacked circuit layer, a plurality of test contact points, and a comparator. The stacked circuit layer includes a plurality of reference capacitors each having a reference capacitance. Each of the test contact points is electrically connecting to an under-test capacitor of an under-test module. The comparator compares the reference capacitance of one of the reference capacitors with an under-test capacitance of the under-test capacitor corresponding to one of the test contact points to measure a range of the under-test capacitance.
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公开(公告)号：US09568543B2
公开(公告)日：2017-02-14
申请号：US14062935
申请日：2013-10-25
发明人： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen
IPC分类号： G01R31/28 , G01R31/3185 , H01L21/66 , H01L27/06
CPC分类号： G01R31/2851 , G01R31/2884 , G01R31/318513 , H01L22/34 , H01L27/0688
摘要： A test structure is provided for testing a semiconductor structure having a plurality of tiers. The test structure includes at least one conductive loop. Each respective conductive loop has ends defining at least one opening between the ends, and is embedded inside one or more of the plurality of tiers in the semiconductor structure. The test structure also includes at least two test pads on each respective conductive loop. The at least two test pads are connected with respective ends of each respective conductive loop. The test structure is configured to permit detection of defects within each of the plurality of tiers in the semiconductor structure if the defects exist, using a testing apparatus.
摘要翻译： 提供了一种用于测试具有多个层的半导体结构的测试结构。 测试结构包括至少一个导电回路。 每个相应的导电回路具有限定端部之间的至少一个开口的端部，并且被嵌入在半导体结构中的多个层中的一个或多个层内。 测试结构还包括在每个相应的导电回路上的至少两个测试焊盘。 至少两个测试焊盘与每个相应的导电回路的相应端连接。 如果存在缺陷，则使用测试装置，将测试结构配置为允许检测半导体结构中的多个层的每一层内的缺陷。
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