公开(公告)号：US10978463B2

公开(公告)日：2021-04-13

申请号：US16748584

申请日：2020-01-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： ShihKuang Yang ,  Yong-Shiuan Tsair ,  Po-Wei Liu ,  Hung-Ling Shih ,  Yu-Ling Hsu ,  Chieh-Fei Chiu ,  Wen-Tuo Huang

IPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/423 ,  H01L21/28 ,  H01L29/78

摘要： A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°

公开(公告)号：US10541245B2

公开(公告)日：2020-01-21

申请号：US16204840

申请日：2018-11-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： ShihKuang Yang ,  Yong-Shiuan Tsair ,  Po-Wei Liu ,  Hung-Ling Shih ,  Yu-Ling Hsu ,  Chieh-Fei Chiu ,  Wen-Tuo Huang

IPC分类号： H01L29/788 ,  H01L27/11521 ,  H01L29/423 ,  H01L21/28 ,  H01L29/78

摘要： A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°

公开(公告)号：US10510544B2

公开(公告)日：2019-12-17

申请号：US15726019

申请日：2017-10-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yu-Ling Hsu ,  Hung-Ling Shih ,  Chieh-Fei Chiu ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair ,  Shihkuang Yang

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L23/31 ,  H01L27/11531 ,  H01L29/423 ,  H01L45/00 ,  H01L27/11521 ,  H01L27/24 ,  H01L27/11548

摘要： A method of manufacturing a non-volatile memory semiconductor device includes forming a plurality of memory cells on a non-volatile memory cell area of a semiconductor substrate, and forming a conductive layer over the plurality of memory cells. A first planarization layer of a planarization material having a viscosity of less than about 1.2 centipoise is formed over the plurality of memory cells. A planarization operation is performed on the first planarization layer and the conductive layer, thereby removing an upper region of the first planarization layer and an upper region of the conductive layer. Portions of a lower region of the conductive layer are completely removed between the memory cells.

公开(公告)号：US20180269299A1

公开(公告)日：2018-09-20

申请号：US15463088

申请日：2017-03-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hung-Wen Hsu ,  Hung-Ling Shih ,  Jiech-Fun Lu

IPC分类号： H01L29/49 ,  H01L27/06 ,  H01L21/311 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66

摘要： A method of manufacturing a semiconductor structure is provided. An interlayer dielectric layer is formed conformally over protruding structures formed over a silicon substrate and a surface of the silicon substrate. Next, a vaporized chemical etching operation is performed to the interlayer dielectric layer, so as to form a gap between two adjacent protruding structures. The gap has a target aspect ratio of at least 4, a top portion of the interlayer dielectric layer above an upper portion of each of the at least two protruding structures is trimmed at a first etching rate, and a bottom portion of the interlayer dielectric layer above a base portion of each of the at least two protruding structures is etched at a second etching rate smaller than the first etching rate, for enlarging the deposition process window and preventing voids from remaining inside a gap filling material in the gap.

公开(公告)号：US09997524B2

公开(公告)日：2018-06-12

申请号：US15272067

申请日：2016-09-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hung-Ling Shih ,  Chieh-Fei Chiu ,  Po-Wei Liu ,  Tsun-Kai Tsao ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair

IPC分类号： H01L29/788 ,  H01L27/11521

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42324

摘要： A memory device includes a substrate. An insulation layer is disposed in a recess in the substrate. A first gate structure is disposed over the substrate and the insulation layer. A first etch stop layer is disposed over the first gate structure. A first oxide layer is disposed over the first etch stop layer. A second etch stop layer is disposed over the first oxide layer. A first contact material is surrounded by and in contact with the first gate structure, first etch stop layer, second etch stop layer, and first oxide layer.

公开(公告)号：US09917003B2

公开(公告)日：2018-03-13

申请号：US13930189

申请日：2013-06-28

申请人： Taiwan Semiconductor Manufacturing Co., LTD.

发明人： Cheng-Hsien Chou ,  Hung-Ling Shih ,  Tsun-Kai Tsao ,  Ming-Huei Shen ,  Kuo-Hwa Tzeng ,  Yeur-Luen Tu

IPC分类号： H01L21/762 ,  H01L21/02

CPC分类号： H01L21/76224 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211

摘要： A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a bottom portion and a top portion. The bottom portion has a lining oxide layer, a negatively-charged liner and a first silicon oxide. The lining oxide layer is peripherally enclosed by the semiconductor substrate, the negatively-charged liner is peripherally enclosed by the lining oxide layer, and the first silicon oxide is peripherally enclosed by the negatively-charged liner. The top portion adjoins the bottom portion, and has a second silicon oxide peripherally enclosed by and contacting the semiconductor substrate.

公开(公告)号：US20160035736A1

公开(公告)日：2016-02-04

申请号：US14445697

申请日：2014-07-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hung-Ling Shih ,  Yong-Shiuan Tsair ,  Tsun-Kai Tsao ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu

IPC分类号： H01L27/115 ,  H01L29/06 ,  H01L29/49 ,  H01L21/321 ,  H01L21/027 ,  H01L21/28 ,  H01L21/762 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825

摘要： The present disclosure relates to a non-volatile memory cell structure, and an associated method. A non-volatile memory cell includes two transistors spaced apart from one another with floating gates connected together by a floating gate bridge. During the operation, the non-volatile memory cell is programmed and erased from one first transistor and read from the other second transistor. Since the floating gates of the two transistors are connected together and insulated from other ambient layers, stored charges can be controlled from the first transistor and affect a threshold of the second transistor.

摘要翻译： 本公开涉及非易失性存储器单元结构以及相关联的方法。 非易失性存储单元包括两个彼此间隔开的晶体管，浮置栅极通过浮栅连接在一起。 在操作期间，非易失性存储单元被编程并从一个第一晶体管擦除并从另一个第二晶体管读取。 由于两个晶体管的浮置栅极连接在一起并与其他环境层绝缘，所以可以从第一晶体管控制存储的电荷并影响第二晶体管的阈值。

公开(公告)号：US20160013195A1

公开(公告)日：2016-01-14

申请号：US14326562

申请日：2014-07-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsun-Kai Tsao ,  Yong-Shiuan Tsair ,  Hung-Ling Shih ,  Po-Wei Liu ,  Wen-Tuo Huang

IPC分类号： H01L27/115 ,  H01L29/788 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L23/528 ,  H01L21/28273 ,  H01L21/32137 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate that includes a first source/drain region and a second source/drain region. The semiconductor structure further includes an erase gate located over the first source/drain region, and a word line and a floating gate located over the semiconductor substrate between the first and second source/drain regions. The floating gate is arranged between the word line and the erase gate. Further, the floating gate includes a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on opposing sides, respectively, of the floating gate. A method of manufacturing the semiconductor structure using a high selectively etch recipe, such as an etch recipe comprised of primarily hydrogen bromide (HBr) and oxygen, is also provided.

摘要翻译： 提供了分离栅闪存单元的半导体结构。 半导体结构包括包括第一源极/漏极区域和第二源极/漏极区域的半导体衬底。 半导体结构还包括位于第一源极/漏极区域上方的擦除栅极以及位于第一和第二源极/漏极区域之间的位于半导体衬底之上的字线和浮置栅极。 浮栅位于字线与擦除栅之间。 此外，浮动栅极包括从浮动栅极的顶表面垂直向上延伸并且分别布置在浮动栅极的相对侧上的一对突起。 还提供了使用高选择性蚀刻配方制造半导体结构的方法，例如主要由溴化氢（HBr）和氧组成的蚀刻配方。

公开(公告)号：US11862535B2

公开(公告)日：2024-01-02

申请号：US17177660

申请日：2021-02-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hung-Ling Shih ,  Wei Chuang Wu ,  Shih Kuang Yang ,  Hsing-Chih Lin ,  Jen-Cheng Liu

IPC分类号： H01L23/48 ,  H01L23/522 ,  H01L21/308 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/308 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/5226

摘要： The present disclosure relates an integrated chip. The integrated chip includes a semiconductor device arranged along a first side of a semiconductor substrate. The semiconductor substrate has one or more sidewalls extending from the first side of the semiconductor substrate to an opposing second side of the semiconductor substrate. A dielectric liner lines the one or more sidewalls of the semiconductor substrate. A through-substrate-via (TSV) is arranged between the one or more sidewalls and is separated from the semiconductor substrate by the dielectric liner. The TSV has a first width at a first distance from the second side and a second width at a second distance from the second side. The first width is smaller than the second width and the first distance is smaller than the second distance.

公开(公告)号：US11652025B2

公开(公告)日：2023-05-16

申请号：US17150048

申请日：2021-01-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hung-Ling Shih ,  Ming Chyi Liu ,  Jiech-Fun Lu

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L27/146

CPC分类号： H01L23/481 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76898 ,  H01L27/14636 ,  H01L27/1464

摘要： In some embodiments, the present disclosure relates to an integrated chip (IC) including a conductive structure disposed within a dielectric structure along a first side of a semiconductor substrate, an insulating structure disposed along inner sidewalls of the semiconductor substrate, the inner sidewalls of the semiconductor substrate extending through the semiconductor substrate, a blocking layer disposed along inner sidewalls of the insulating structure, and a through-substrate via (TSV) comprising a first portion and a second portion, the first portion extending from a second side of the semiconductor substrate to a horizontally-extending surface of the insulating structure that protrudes outward from the inner sidewalls of the insulating structure, the second portion extending from the first portion to the conductive structure and has a maximum width less than that of the first portion.