-
公开(公告)号：US11315972B2
公开(公告)日：2022-04-26
申请号：US17095994
申请日：2020-11-12
发明人： Hung-Wen Hsu , Jiech-Fun Lu , Yeur-Luen Tu , U-Ting Chen , Shu-Ting Tsai , Hsiu-Yu Cheng
IPC分类号： H01L27/14 , H01L27/146
摘要： A backside illumination (BSI) image sensor and a method of forming the same are provided. A method includes forming a plurality of photosensitive pixels in a substrate, the substrate having a first surface and a second surface, the second surface being opposite the first surface, the substrate having one or more active devices on the first surface. A first portion of the second surface is protected. A second portion of the second surface is patterned to form recesses in the substrate. An anti-reflective layer is formed on sidewalls of the recesses. A metal grid is formed over the second portion of the second surface, the anti-reflective layer being interposed between the substrate and the metal grid.
-
公开(公告)号：US20200091223A1
公开(公告)日：2020-03-19
申请号：US16693627
申请日：2019-11-25
发明人： Ching-Chung Su , Hung-Wen Hsu , Jiech-Fun Lu , Shih-Pei Chou
IPC分类号： H01L27/146
摘要： The present disclosure, in some embodiments, relates to method of forming an integrated chip. The method may be performed by forming an image sensing element within a substrate. A dry etching process is performed on the substrate to form a plurality of intermediate protrusions defined by the substrate. A wet etching process is performed on the plurality of intermediate protrusions to form a plurality of protrusions from the plurality of intermediate protrusions.
-
公开(公告)号：US20180269299A1
公开(公告)日：2018-09-20
申请号：US15463088
申请日：2017-03-20
发明人： Hung-Wen Hsu , Hung-Ling Shih , Jiech-Fun Lu
IPC分类号： H01L29/49 , H01L27/06 , H01L21/311 , H01L29/423 , H01L29/40 , H01L29/66
摘要： A method of manufacturing a semiconductor structure is provided. An interlayer dielectric layer is formed conformally over protruding structures formed over a silicon substrate and a surface of the silicon substrate. Next, a vaporized chemical etching operation is performed to the interlayer dielectric layer, so as to form a gap between two adjacent protruding structures. The gap has a target aspect ratio of at least 4, a top portion of the interlayer dielectric layer above an upper portion of each of the at least two protruding structures is trimmed at a first etching rate, and a bottom portion of the interlayer dielectric layer above a base portion of each of the at least two protruding structures is etched at a second etching rate smaller than the first etching rate, for enlarging the deposition process window and preventing voids from remaining inside a gap filling material in the gap.
-
公开(公告)号：US11139239B2
公开(公告)日：2021-10-05
申请号：US16589395
申请日：2019-10-01
发明人： Hung-Wen Hsu , Jiech-Fun Lu , Kai Tzeng , Wei-Li Huang
IPC分类号： H01L23/522 , H01L49/02 , H01L21/768 , H01L23/532 , H01L23/528
摘要： Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including an interconnect structure overlying a substrate. The interconnect structure has a plurality of metal layers overlying over the substrate. A first dielectric layer overlies an uppermost surface of the interconnect structure. The first dielectric layer has opposing sidewalls defining a trench. A first magnetic layer is disposed within the trench and conformally extends along the opposing sidewalls. Conductive wires are disposed within the trench and overlie the first magnetic layer. A second magnetic layer overlies the first magnetic layer and the conductive wires. The second magnetic layer laterally extends from over a first sidewall of the opposing sidewalls to a second sidewall of the opposing sidewalls.
-
公开(公告)号：US20210098371A1
公开(公告)日：2021-04-01
申请号：US16589395
申请日：2019-10-01
发明人： Hung-Wen Hsu , Jiech-Fun Lu , Kai Tzeng , Wei-Li Huang
IPC分类号： H01L23/522 , H01L49/02 , H01L23/528 , H01L23/532 , H01L21/768
摘要： Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including an interconnect structure overlying a substrate. The interconnect structure has a plurality of metal layers overlying over the substrate. A first dielectric layer overlies an uppermost surface of the interconnect structure. The first dielectric layer has opposing sidewalls defining a trench. A first magnetic layer is disposed within the trench and conformally extends along the opposing sidewalls. Conductive wires are disposed within the trench and overlie the first magnetic layer. A second magnetic layer overlies the first magnetic layer and the conductive wires. The second magnetic layer laterally extends from over a first sidewall of the opposing sidewalls to a second sidewall of the opposing sidewalls.
-
公开(公告)号：US20210376053A1
公开(公告)日：2021-12-02
申请号：US16884319
申请日：2020-05-27
发明人： Hung-Wen Hsu , Po-Han Huang , Wei-Li Huang
摘要： The present disclosure relates to, in part, an inductor structure that includes an etch stop layer arranged over an interconnect structure overlying a substrate. A magnetic structure includes a plurality of stacked layers is arranged over the etch stop layer. The magnetic structure includes a bottommost layer that is wider than a topmost layer. A first conductive wire and a second conductive wire extend in parallel over the magnetic structure. The magnetic structure is configured to modify magnetic fields generated by the first and second conductive wires. A pattern enhancement layer is arranged between the bottommost layer of the magnetic structure and the etch stop layer. The pattern enhancement layer has a first thickness, and the bottommost layer of the magnetic structure has a second thickness that is less than the first thickness.
-
公开(公告)号：US10304898B2
公开(公告)日：2019-05-28
申请号：US16190608
申请日：2018-11-14
发明人： Ching-Chung Su , Hung-Wen Hsu , Jiech-Fun Lu , Shih-Pei Chou
IPC分类号： H01L27/146
摘要： In some embodiments, the present disclosure relates to an image sensor device. The image sensor device includes an image sensing element disposed within a substrate. A plurality of protrusions are arranged along a first side of the substrate over the image sensing element. The plurality of protrusions respectively include a sidewall having a first segment oriented at a first angle and a second segment over the first segment. The second segment is oriented at a second angle that is larger than the first angle. One or more absorption enhancement layers are arranged over and between the plurality of protrusions. The first angle and the second angle are acute angles measured through the substrate with respect to a horizontal plane that is parallel to a second side of the substrate opposite the first side.
-
公开(公告)号：US20190103437A1
公开(公告)日：2019-04-04
申请号：US16190608
申请日：2018-11-14
发明人： Ching-Chung Su , Hung-Wen Hsu , Jiech-Fun Lu , Shih-Pei Chou
IPC分类号： H01L27/146
摘要： In some embodiments, the present disclosure relates to an image sensor device. The image sensor device includes an image sensing element disposed within a substrate. A plurality of protrusions are arranged along a first side of the substrate over the image sensing element. The plurality of protrusions respectively include a sidewall having a first segment oriented at a first angle and a second segment over the first segment. The second segment is oriented at a second angle that is larger than the first angle. One or more absorption enhancement layers are arranged over and between the plurality of protrusions. The first angle and the second angle are acute angles measured through the substrate with respect to a horizontal plane that is parallel to a second side of the substrate opposite the first side.
-
公开(公告)号：US10084056B1
公开(公告)日：2018-09-25
申请号：US15463088
申请日：2017-03-20
发明人： Hung-Wen Hsu , Hung-Ling Shih , Jiech-Fun Lu
IPC分类号： H01L21/302 , H01L29/49 , H01L27/06 , H01L21/311 , H01L29/423 , H01L29/40 , H01L29/66 , H01L21/768
摘要： A method of manufacturing a semiconductor structure is provided. An interlayer dielectric layer is formed conformally over protruding structures formed over a silicon substrate and a surface of the silicon substrate. Next, a vaporized chemical etching operation is performed to the interlayer dielectric layer, so as to form a gap between two adjacent protruding structures. The gap has a target aspect ratio of at least 4, a top portion of the interlayer dielectric layer above an upper portion of each of the at least two protruding structures is trimmed at a first etching rate, and a bottom portion of the interlayer dielectric layer above a base portion of each of the at least two protruding structures is etched at a second etching rate smaller than the first etching rate, for enlarging the deposition process window and preventing voids from remaining inside a gap filling material in the gap.
-
公开(公告)号：US09991303B2
公开(公告)日：2018-06-05
申请号：US14658465
申请日：2015-03-16
发明人： Hung-Wen Hsu , Ching-Chung Su , Cheng-Hsien Chou , Jiech-Fun Lu , Shih-Pei Chou , Yeur-Luen Tu
IPC分类号： H01L27/146
CPC分类号： H01L27/14623 , H01L27/1462 , H01L27/14621 , H01L27/14627 , H01L27/1463 , H01L27/14687 , H01L27/14689
摘要： An image sensor structure is provided. The image sensor device structure includes a substrate, and the substrate includes an array region and a peripheral region. The image sensor device structure includes an anti-reflection layer formed on the substrate and a buffer layer formed on the anti-reflection layer. The image sensor device structure includes a first etch stop layer formed on the buffer layer and a metal grid structure formed on the first etch stop layer. The image sensor device structure also includes a dielectric layer formed on the metal grid structure.
-
-
-
-
-
-
-
-
-
搜索结果
23 条记录 (耗时 0.02 秒)
