公开(公告)号：US20190196322A1

公开(公告)日：2019-06-27

申请号：US15851829

申请日：2017-12-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiang Lin ,  Chien-Cheng Chen ,  Hsin-Chang Lee ,  Chia-Jen Chen ,  Pei-Cheng Hsu ,  Yih-Chen Su ,  Gaston Lee ,  Tran-Hui Shen

IPC: G03F1/24 ,  G03F1/54 ,  G03F7/20

CPC classification number: G03F1/24 ,  G03F1/54 ,  G03F7/2004

Abstract: A lithography mask includes a substrate, a reflective structure disposed over a first side of the substrate, and a patterned absorber layer disposed over the reflective structure. The lithography mask includes a first region and a second region that surrounds the first region in a top view. The patterned absorber layer is located in the first region. A substantially non-reflective material is located in the second region. The lithography mask is formed by forming a reflective structure over a substrate, forming an absorber layer over the reflective structure, defining a first region of the lithography mask, and defining a second region of the lithography mask. The defining of the first region includes patterning the absorber layer. The second region is defined to surround the first region in a top view. The defining of the second region includes forming a substantially non-reflective material in the second region.

公开(公告)号：US10274847B2

公开(公告)日：2019-04-30

申请号：US15708800

申请日：2017-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren Zi ,  Chin-Hsiang Lin ,  Ching-Yu Chang ,  Joy Cheng

IPC: G03F7/20 ,  G03F7/16 ,  H01L21/027 ,  G03F7/32 ,  G03F7/039 ,  G03F7/038 ,  G03F7/38 ,  G03F7/40 ,  G03F7/30 ,  G03F7/06

Abstract: A photo-sensitive layer is applied over a wafer. The photo-sensitive layer is exposed. In some embodiments, the photo-sensitive layer is exposed to EUV light. The photo-sensitive layer is baked. The photo-sensitive layer is developed. Humidity is introduced in at least one of: the applying, the baking, or the developing.

公开(公告)号：US20190094716A1

公开(公告)日：2019-03-28

申请号：US16202860

申请日：2018-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren Zi ,  Chin-Hsiang Lin ,  Ching-Yu Chang ,  Joy Cheng

IPC: G03F7/20 ,  G03F7/038 ,  H01L21/027 ,  G03F7/039 ,  G03F7/06 ,  G03F7/16 ,  G03F7/32 ,  G03F7/40 ,  G03F7/30 ,  G03F7/38

Abstract: A photo-sensitive layer is applied over a wafer. The photo-sensitive layer is exposed. In some embodiments, the photo-sensitive layer is exposed to EUV light. The photo-sensitive layer is baked. The photo-sensitive layer is developed. Humidity is introduced in at least one of: the applying, the baking, or the developing.

公开(公告)号：US20190086818A1

公开(公告)日：2019-03-21

申请号：US15708800

申请日：2017-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren Zi ,  Chin-Hsiang Lin ,  Ching-Yu Chang ,  Joy Cheng

IPC: G03F7/20 ,  G03F7/16 ,  G03F7/38 ,  G03F7/32 ,  G03F7/039 ,  G03F7/038 ,  H01L21/027

Abstract: A photo-sensitive layer is applied over a wafer. The photo-sensitive layer is exposed. In some embodiments, the photo-sensitive layer is exposed to EUV light. The photo-sensitive layer is baked. The photo-sensitive layer is developed. Humidity is introduced in at least one of: the applying, the baking, or the developing.

公开(公告)号：US10163648B2

公开(公告)日：2018-12-25

申请号：US15599851

申请日：2017-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Han Lai ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3105 ,  G03F7/11 ,  B05D3/10 ,  C09D133/10 ,  C08L33/10 ,  C09D133/12 ,  B05D3/06 ,  C09D133/08 ,  C08L33/12 ,  C09D135/02

Abstract: Provided is a material composition and method for that includes providing a primer material including a surface interaction enhancement component, and a cross-linkable component. A cross-linking process is performed on the deposited primer material. The cross-linkable component self-cross-links in response to the cross-linking process to form a cross-linked primer material. The cross-lined primer material can protect an underlying layer while performing at least one process on the cross-linked primer material.

公开(公告)号：US20180335697A1

公开(公告)日：2018-11-22

申请号：US15597309

申请日：2017-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Siao-Shan Wang ,  Chen-Yu Liu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/09 ,  H01L21/027 ,  G03F7/42 ,  G03F7/039 ,  G03F7/038 ,  G03F7/16 ,  G03F7/095 ,  G03F7/38 ,  G03F7/20 ,  G03F7/32

CPC classification number: G03F7/094 ,  G03F7/091 ,  G03F7/095 ,  G03F7/11 ,  H01L21/0274

Abstract: The present disclosure provides a method for lithography patterning in accordance with some embodiments. The method includes forming a material layer over a substrate, wherein the material layer is soluble in a solvent; forming a blocking layer on the material layer; and forming a photoresist layer on the blocking layer, wherein the photoresist layer includes a photosensitive material dissolved in the solvent. The method further includes exposing the photoresist layer; and developing the photoresist layer in a developer.

公开(公告)号：US10049918B2

公开(公告)日：2018-08-14

申请号：US15395310

申请日：2016-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Cheng Hung ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ta-Ching Yu ,  Yung-Sung Yen ,  Ziwei Fang ,  Tsai-Sheng Gau ,  Chin-Hsiang Lin ,  Kuei-Shun Chen

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/033 ,  H01L21/3115

Abstract: Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature having an associated horizontally-defined characteristic; tuning an etching process to direct etching species in a substantially horizontal direction relative to a horizontal surface of the wafer, such that the etching process horizontally removes portions of the patterned hard mask layer, thereby modifying the horizontally-defined characteristic of the hard mask feature; and forming an integrated circuit feature that corresponds with the hard mask feature having the modified horizontally-defined characteristic. Horizontally-defined characteristic can include a length, a width, a line edge roughness, a line width roughness, a line end profile, other horizontally-defined characteristics, or combinations thereof. In some implementations, the directional patterning method disclosed herein can achieve oblique interconnects and/or slot (rectangular) via interconnects.

公开(公告)号：US20180149959A1

公开(公告)日：2018-05-31

申请号：US15670183

申请日：2017-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yue Lin ,  Hsin-Chang Lee ,  Chia-Jen Chen ,  Chih-Cheng Lin ,  Anthony Yen ,  Chin-Hsiang Lin

IPC: G03F1/24 ,  G03F1/54 ,  G03F1/42 ,  G03F1/26 ,  G03F1/48

CPC classification number: G03F1/24 ,  G03F1/26 ,  G03F1/42 ,  G03F1/48 ,  G03F1/50 ,  G03F1/54

Abstract: A lithography mask includes a substrate that contains a low thermal expansion material (LTEM). A reflective structure is disposed over a first side of the substrate. An absorber layer is disposed over the reflective structure. The absorber layer contains one or more first overlay marks. A conductive layer is disposed over a second side of the substrate, the second side being opposite the first side. The conductive layer contains portions of one or more second overlay marks. In some embodiments, the lithography mask includes an EUV lithography mask.

公开(公告)号：US20180090370A1

公开(公告)日：2018-03-29

申请号：US15395310

申请日：2016-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Cheng Hung ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ta-Ching Yu ,  Yung-Sung Yen ,  Ziwei Fang ,  Tsai-Sheng Gau ,  Chin-Hsiang Lin ,  Kuei-Shun Chen

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3115

CPC classification number: H01L21/76816 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/31155

Abstract: Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature having an associated horizontally-defined characteristic; tuning an etching process to direct etching species in a substantially horizontal direction relative to a horizontal surface of the wafer, such that the etching process horizontally removes portions of the patterned hard mask layer, thereby modifying the horizontally-defined characteristic of the hard mask feature; and forming an integrated circuit feature that corresponds with the hard mask feature having the modified horizontally-defined characteristic. Horizontally-defined characteristic can include a length, a width, a line edge roughness, a line width roughness, a line end profile, other horizontally-defined characteristics, or combinations thereof. In some implementations, the directional patterning method disclosed herein can achieve oblique interconnects and/or slot (rectangular) via interconnects.

公开(公告)号：US09776216B2

公开(公告)日：2017-10-03

申请号：US14092533

申请日：2013-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Weibo Yu ,  Kuo-Sheng Chuang ,  Wen-Yu Ku ,  Chin-Hsiang Lin

IPC: B08B3/02 ,  B08B17/02 ,  H01L21/67 ,  B05B15/02

CPC classification number: B08B3/02 ,  B05B15/555 ,  B08B17/025 ,  H01L21/67051

Abstract: A dispensing method is disclosed that includes the following steps: a cleaning sleeve is provided to surround a spray member. A first fluid is previously dispensed from a first fluid outlet of the spray member. A second fluid is sprayed from a second fluid outlet of the cleaning sleeve to clean the spray member. The cleaning sleeve is opened or slid away from the spray member, such that the first fluid outlet of the spray member is exposed to a substrate. The first fluid is dispensed from the first fluid outlet of the spray member to the substrate.