公开(公告)号：US20180033796A1

公开(公告)日：2018-02-01

申请号：US15219497

申请日：2016-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Ming Lee ,  Po-Wei Liu ,  Chiang-Ming Chuang ,  Yung-Lung Hsu ,  Hsin-Chi Chen

IPC: H01L27/115 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/11521 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53271 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/42368 ,  H01L2924/1438

Abstract: A semiconductor device includes a pair of erase gate lines, a pair of control gate lines and a pair of word lines. The pair of control gate lines are disposed on the erase gate lines. Each one of the control gate lines includes a plurality of segments between which portions of one of the pair of erase gate lines are seen in a plan view. In a plan view of the semiconductor device, the pair of word lines are disposed between the control gate lines and extending along edges of the control gate lines.

公开(公告)号：US09768182B2

公开(公告)日：2017-09-19

申请号：US15158517

申请日：2016-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chiang-Ming Chuang ,  Chien-Hsuan Liu ,  Chih-Ming Lee ,  Kun-Tsang Chuang ,  Hung-Che Liao ,  Hsin-Chi Chen

IPC: H01L27/11 ,  H01L27/11521 ,  H01L23/535 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  H01L23/535 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11575 ,  H01L29/0649 ,  H01L29/42328

Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.

公开(公告)号：US09728543B1

公开(公告)日：2017-08-08

申请号：US15236533

申请日：2016-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Ming Pan ,  Chiang-Ming Chuang ,  Kun-Tsang Chuang ,  Po-Wei Liu ,  Yong-Shiuan Tsair

IPC: H01L29/788 ,  H01L27/11526 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/11521

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of fabricating a semiconductor structure includes the following steps. A first dummy gate structure and a second dummy gate structure are formed on a semiconductor substrate. A recess is formed next to the first and the second dummy gate structure and in the semiconductor substrate. A pair of first spacers is formed adjacent to the first dummy gate structure. A pair of second spacers is formed adjacent to the second dummy gate structure. One of the first spacers extends from a first sidewall of the first dummy gate structure to a first inner sidewall of the recess. One of the second spacers extends from a second sidewall of the second dummy gate structure to a second inner sidewall of the recess. A first isolation layer is formed on a bottom surface of the recess. A first conducting layer is formed on the first isolation layer.