公开(公告)号：US11527504B2

公开(公告)日：2022-12-13

申请号：US16989461

申请日：2020-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Fu Shih ,  Chun-Yen Lo ,  Cheng-Lin Huang ,  Wen-Ming Chen ,  Chien-Ming Huang ,  Yuan-Fu Liu ,  Yung-Chiuan Cheng ,  Wei-Chih Huang ,  Chen-Hsun Liu ,  Chien-Pin Chan ,  Yu-Nu Hsu ,  Chi-Hung Lin ,  Te-Hsun Pang ,  Chin-Yu Ku

IPC: H01L23/00 ,  C25D5/12 ,  C25D5/50 ,  C25D7/12 ,  C25D17/12 ,  C25D21/10 ,  C25D17/00 ,  H01L23/31 ,  C25D3/12 ,  C25D3/38 ,  C25D3/60

Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

公开(公告)号：US11355406B2

公开(公告)日：2022-06-07

申请号：US16895415

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Lin Huang ,  Jung-Hua Chang ,  Jy-Jie Gau ,  Jing-Cheng Lin

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065

Abstract: A package includes a device die, a through-via having a sand timer profile, and a molding material molding the device die and the through-via therein, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die. A plurality of redistribution lines (RDLs) extends into the dielectric layer to electrically couple to the device die and the through-via.

公开(公告)号：US10535554B2

公开(公告)日：2020-01-14

申请号：US15725558

申请日：2017-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Sheng Tang ,  Fu-Chen Chang ,  Cheng-Lin Huang ,  Chun-Yen Lo ,  Wen-Ming Chen ,  Kuo-Chio Liu

IPC: H01L23/495 ,  H01L23/522 ,  H01L21/304 ,  H01L21/56 ,  H01L21/768 ,  H01L21/683 ,  H01L21/67 ,  H01L23/00 ,  H01L23/48 ,  H01L21/78 ,  H01L23/498 ,  H01L25/10 ,  H01L23/58 ,  H01L25/065 ,  H01L25/00

Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies. In addition, a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening.