公开(公告)号：US10861943B2

公开(公告)日：2020-12-08

申请号：US16216874

申请日：2018-12-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/20 ,  H01L29/778 ,  H01L29/66

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a first GaN-based alloy layer having a top side and disposed on the GaN layer; a second GaN-based alloy layer disposed on the first GaN-based alloy layer, wherein the second GaN-based alloy layer covers a first portion of the top side; and a source contact structure, a drain contact structure, and a gate contact structure, wherein the source, drain, and gate contact structures are supported by the first GaN-based alloy layer.

公开(公告)号：US20200064394A1

公开(公告)日：2020-02-27

申请号：US16400336

申请日：2019-05-01

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: G01R31/26 ,  G01R27/26

Abstract: A method includes applying a DC stress condition to a transistor for a predetermined stress time, measuring an impedance of the transistor after the predetermined stress time, and repeating the application of the DC stress condition and the measurement of the impedance until the measured impedance exceeds an impedance threshold or a total stress time exceeds a time threshold, where the DC stress condition includes applying a non-zero drain voltage signal to a drain terminal of the transistor, applying a gate voltage signal to a gate terminal of the transistor, and applying a non-zero source current signal to a source terminal of the transistor.

公开(公告)号：US10014231B1

公开(公告)日：2018-07-03

申请号：US15439191

申请日：2017-02-22

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Sameer Pendharkar

IPC: H01L29/06 ,  H01L29/20 ,  G01R31/12 ,  H01L21/66 ,  H01L23/544 ,  H01L29/40 ,  H01L29/417 ,  H01L27/088 ,  G01R31/28

Abstract: A first set of test structures for a gallium nitride (GaN) transistor that includes N field plates is disclosed, where N is an integer and X is an integer between 0 and N inclusive. A test structure TSX of the first set of test structures includes a GaN substrate, a dielectric material overlying the GaN substrate, a respective source contact abutting the GaN substrate and a respective drain contact abutting the GaN substrate. The test structure TSX also includes a respective gate overlying the substrate and lying between the respective source contact and the respective drain contact and X respective field plates corresponding to X of the N field plates of the GaN transistor, the X respective field plates including field plates that are nearest to the GaN substrate.

公开(公告)号：US09476933B2

公开(公告)日：2016-10-25

申请号：US14547849

申请日：2014-11-19

Applicant: Texas Instruments Incorporated

Inventor： Jungwoo Joh ,  Srikanth Krishnan ,  Sameer Pendharkar

IPC: G01R31/02 ,  G01R31/26 ,  H01L29/778 ,  H01L29/20

CPC classification number: G01R31/2621 ,  H01L29/2003 ,  H01L29/7787

Abstract: A method includes coupling a gate pulse generator to a gate terminal of a power transistor device under test, coupling a drain pulse generator to a drain terminal of the power transistor device under test; for a first set of test conditions, activating the drain pulse generator for each of the test conditions to apply a voltage pulse to the drain terminal, and for each of the test conditions, applying a voltage pulse to the gate terminal, the gate pulse rising only after the drain pulse falls below a predetermined threshold; for a second set of test conditions, applying a voltage pulse to the drain terminal, and applying a voltage pulse to the gate terminal, the drain pulse generator and the gate pulse generator both being active so that there is some overlap; and measuring the drain current into the power transistor device under test. An apparatus is disclosed.

Abstract translation: 一种方法包括将栅极脉冲发生器耦合到被测功率晶体管器件的栅极端子，将漏极脉冲发生器耦合到被测功率晶体管器件的漏极端子; 对于第一组测试条件，激活用于每个测试条件的漏极脉冲发生器以向漏极端施加电压脉冲，并且对于每个测试条件，向栅极端施加电压脉冲，门脉冲上升 仅在漏极脉冲下降到预定阈值以下之前; 对于第二组测试条件，向漏极端子施加电压脉冲，并向栅极端施加电压脉冲，漏极脉冲发生器和栅极脉冲发生器都处于活动状态，使得存在一些重叠; 并测量进入被测功率晶体管器件的漏极电流。 公开了一种装置。

公开(公告)号：US09112011B2

公开(公告)日：2015-08-18

申请号：US14537455

申请日：2014-11-10

Applicant: Texas Instruments Incorporated

Inventor： Asad Mahmood Haider ,  Jungwoo Joh

IPC: H01L31/0256 ,  H01L29/778 ,  H01L29/51 ,  H01L29/66 ,  H01L29/20 ,  H01L21/28 ,  H01L21/285 ,  H01L29/49 ,  H01L29/45

CPC classification number: H01L29/7787 ,  H01L21/28264 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/452 ,  H01L29/4975 ,  H01L29/518 ,  H01L29/66462

Abstract: A semiconductor device may be formed by forming a silicon-containing gate dielectric layer over a semiconductor layer. A gate metal layer is formed over the gate dielectric layer; the gate metal layer includes 2 atomic percent to 10 atomic percent silicon during formation. The gate metal layer is patterned to form a metal gate. Source and drain contact holes are subsequently formed, and contact metal is formed and patterned in the contact holes. A subsequent contact anneal heats the contact metal and gate for at least 30 seconds at a temperature of at least 750° C.

Abstract translation: 可以通过在半导体层上形成含硅栅极电介质层来形成半导体器件。 栅极金属层形成在栅极介质层上; 栅极金属层在形成期间包括2原子％至10原子％的硅。 栅极金属层被图案化以形成金属栅极。 随后形成源极和漏极接触孔，并在接触孔中形成接触金属并图案化。 随后的接触退火在至少750℃的温度下加热接触金属和栅极至少30秒。

公开(公告)号：US20250048667A1

公开(公告)日：2025-02-06

申请号：US18361997

申请日：2023-07-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ujwal Radhakrishna ,  Zhikai Tang ,  Johan Strydom ,  Jungwoo Joh

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/47 ,  H01L29/872

Abstract: The present disclosure generally relates to a semiconductor device that includes a gate electrical contact that forms junctions with different energy barrier heights to a gate layer. In an example, a semiconductor device includes a semiconductor substrate, a drain electrical contact, a source electrical contact, a barrier layer, a gate layer, and a gate electrical contact. The drain and source electrical contacts are on the semiconductor substrate. The barrier layer is over a channel region of the semiconductor substrate between the drain and source electrical contacts. The gate layer is over the barrier layer. The gate layer includes first and second semiconductor portions. The gate electrical contact contacts the gate layer. The gate electrical contact includes first and second metal portions. The first and second metal portions form first and second junctions with the first and second semiconductor portions, respectively. The first and second junctions have different energy barrier heights.

公开(公告)号：US12113062B2

公开(公告)日：2024-10-08

申请号：US17137784

申请日：2020-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Tipirneni ,  Maik Peter Kaufmann ,  Michael Lueders ,  Jungwoo Joh

IPC: H01L27/06 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L49/02 ,  H02M3/156 ,  H03K3/037

CPC classification number: H01L27/0629 ,  H01L21/8252 ,  H01L27/0605 ,  H01L28/60 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7781 ,  H02M3/156 ,  H03K3/0377

Abstract: The present invention provides a capacitor having a first structure made of a metal layer and a second structure made of the same metal layer and a dielectric layer between the first and the second metal structure, wherein the dielectric layer has a relative permittivity greater than 4, in particular greater than 6. It also provides a monolithically integrated circuit including such a capacitor and optionally other components. A method of manufacturing such a capacitor is also provided.

公开(公告)号：US20240274705A1

公开(公告)日：2024-08-15

申请号：US18625366

申请日：2024-04-03

Applicant: Texas Instruments Incorporated

Inventor： Chang Soo Suh ,  Jungwoo Joh ,  Dong Seup Lee ,  Shoji Wada ,  Karen Hildegard Ralston Kirmse

IPC: H01L29/778 ,  B82Y30/00 ,  B82Y40/00 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/66462 ,  B82Y30/00 ,  B82Y40/00

Abstract: A semiconductor device includes a gallium nitride based low threshold depletion mode transistor (GaN FET) with a threshold potential between −10 volts and −0.5 volts. The GaN FET has a channel layer of III-N semiconductor material including gallium and nitrogen that supports a two-dimensional electron gas (2DEG). The GaN FET has a barrier layer of III-N semiconductor material including aluminum and nitrogen over the channel layer. The GaN FET further has a p-type gate of III-N semiconductor material including gallium and nitrogen. A bottom surface of the gate, adjacent to the barrier layer, does not extend past a top surface of the barrier layer, located opposite from the channel layer. The GaN FET is free of a dielectric layer between the gate and the barrier layer.

公开(公告)号：US11978790B2

公开(公告)日：2024-05-07

申请号：US17108892

申请日：2020-12-01

Applicant: Texas Instruments Incorporated

Inventor： Chang Soo Suh ,  Jungwoo Joh ,  Dong Seup Lee ,  Shoji Wada ,  Karen Hildegard Ralston Kirmse

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  B82Y30/00 ,  B82Y40/00

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/66462 ,  B82Y30/00 ,  B82Y40/00

Abstract: A semiconductor device includes a gallium nitride based low threshold depletion mode transistor (GaN FET) with a threshold potential between −10 volts and −0.5 volts. The GaN FET has a channel layer of III-N semiconductor material including gallium and nitrogen that supports a two-dimensional electron gas (2DEG). The GaN FET has a barrier layer of III-N semiconductor material including aluminum and nitrogen over the channel layer. The GaN FET further has a p-type gate of III-N semiconductor material including gallium and nitrogen. A bottom surface of the gate, adjacent to the barrier layer, does not extend past a top surface of the barrier layer, located opposite from the channel layer. The GaN FET is free of a dielectric layer between the gate and the barrier layer.

公开(公告)号：US20240120383A1

公开(公告)日：2024-04-11

申请号：US18543738

申请日：2023-12-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Qhalid Fareed ,  Sridhar Seetharaman ,  Jungwoo Joh ,  Chang Soo Suh

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/2003

Abstract: An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.