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公开(公告)号：US11798630B2
公开(公告)日：2023-10-24
申请号：US17407903
申请日：2021-08-20
Applicant: STMicroelectronics S.r.l.
Inventor： Marcella Carissimi , Fabio Enrico Carlo Disegni , Chantal Auricchio , Cesare Torti , Davide Manfre' , Laura Capecchi , Emanuela Calvetti , Stefano Zanchi
CPC classification number: G11C16/102 , G11C7/04 , G11C16/24 , G11C16/28 , G11C16/30
Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.
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22.发明授权公开(公告)号：US11756614B2
公开(公告)日：2023-09-12
申请号：US17657861
申请日：2022-04-04
Applicant: STMicroelectronics S.r.l.
CPC classification number: G11C13/0004 , G11C7/02 , G11C7/06 , G11C13/004 , G11C13/0026 , G11C13/0028 , G11C13/0069
Abstract: A phase-change memory device column decoder is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.
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23.发明授权公开(公告)号：US11328768B2
公开(公告)日：2022-05-10
申请号：US17119979
申请日：2020-12-11
Applicant: STMicroelectronics S.r.l.
Abstract: In an embodiment, the column decoder of a PCM device is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.
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公开(公告)号：US11049561B2
公开(公告)日：2021-06-29
申请号：US16903264
申请日：2020-06-16
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Federico Goller , Cesare Torti , Marcella Carissimi , Emanuela Calvetti
Abstract: A method for programming a phase-change-memory device of a differential type comprises, in a first programming mode, supplying, during a first time interval, a same first programming current, of a type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said first programming current; and, in a second programming mode, supplying, during a second time interval, a same second programming current, of the other type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said second programming current, thus completing, in just two time steps, writing of a logic word in the memory device.
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Patent Agency Ranking
25.发明申请公开(公告)号：US20210193220A1
公开(公告)日：2021-06-24
申请号：US17119979
申请日：2020-12-11
Applicant: STMicroelectronics S.r.l.
Abstract: In an embodiment, the column decoder of a PCM device is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.
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公开(公告)号：US20180240519A1
公开(公告)日：2018-08-23
申请号：US15797732
申请日：2017-10-30
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Manfre , Cesare Torti , Fabio Enrico Carlo Disegni
IPC: G11C13/00
CPC classification number: G11C13/0038 , G11C8/16 , G11C13/0004 , G11C13/0023
Abstract: An embodiment memory device includes a memory array having a plurality of bit lines, a low-voltage connection path configured to connect, in an operational phase of the device, an access terminal to a selected local bit line of the plurality of bit lines, and a high-voltage connection path configured to connect, in the operational phase of the device, the access terminal to the selected local bit line, in parallel with the low-voltage connection path.
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公开(公告)号：US20180151223A1
公开(公告)日：2018-05-31
申请号：US15639540
申请日：2017-06-30
Applicant: STMicroelectronics S.r.l.
Inventor： Cesare Torti , Fabio Enrico Carlo Disegni , Davide Manfre' , Massimo Fidone
CPC classification number: G11C13/0028 , G11C8/08 , G11C13/0004 , G11C13/0038 , G11C13/004 , G11C13/0069 , H01L27/2436 , H01L29/7841 , H01L45/06
Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.
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公开(公告)号：US09099190B2
公开(公告)日：2015-08-04
申请号：US14305482
申请日：2014-06-16
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Cesare Torti
Abstract: A non-volatile memory device includes a sense amplifier for comparing a conduction current of a selected one of a plurality of memory cells with a reference current. The sense amplifier includes an amplification stage having a first input terminal for receiving a first comparison voltage, a second input terminal for receiving a reference value, and an output terminal for providing a second comparison voltage. A buffer stage has an output terminal for providing a comparison current according to a difference between the conduction current and the reference current, and an input terminal for stabilizing the first comparison voltage at the reference value and the second comparison voltage at a comparison value unbalanced with respect to the reference value according to the comparison current. A latching stage indicates a logic level stored in the memory cell according to a difference between the comparison value and the reference value.
Abstract translation: 非易失性存储器件包括读出放大器，用于将多个存储器单元中所选择的一个存储器单元的导通电流与参考电流进行比较。 读出放大器包括具有用于接收第一比较电压的第一输入端子，用于接收基准值的第二输入端子和用于提供第二比较电压的输出端子的放大级。 缓冲级具有输出端子，用于根据导通电流和参考电流之间的差异提供比较电流;以及输入端子，用于使参考值处的第一比较电压和第二比较电压以不平衡的比较值稳定， 根据比较电流对参考值的影响。 锁存级根据比较值和参考值之间的差异指示存储在存储单元中的逻辑电平。
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公开(公告)号：US08913439B2
公开(公告)日：2014-12-16
申请号：US14256034
申请日：2014-04-18
Applicant: Stmicroelectronics S.R.L.
Inventor： Cesare Torti
IPC: G11C11/4091 , G11C11/4094 , G11C7/12 , G11C16/24 , G11C16/26
Abstract: An electrically erasable and programmable non-volatile memory device includes memory cells arranged in rows and columns, and each column of memory cells is associated with a respective local bit line. The local bit lines are divided into packets of local bit lines, each packet of local bit lines associated with a respective main bit line. Each local bit line is selectively couplable to the respective main bit line by a corresponding selector. Each local bit line is selectively couplable to a reference terminal, for receiving a reference voltage, by a corresponding discharge selector. Each discharge selector is active when the memory device is in a standby state. The non-volatile memory device further includes biasing circuitry to bias each main bit line to a pre-charge voltage during operation, and reading circuitry to select and access a group of memory cells during reading operations.
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