Frequency selective attenuator for optimized radio frequency coexistence

    公开(公告)号:US11463064B2

    公开(公告)日:2022-10-04

    申请号:US16706433

    申请日:2019-12-06

    摘要: A wireless transceiver including a receiver circuit coupled to an RF transceiver node, a tunable notch filter coupled between the RF transceiver node and a reference node, and a controller that programs the tunable notch filter with a selected blocker frequency and that selectively enables the tunable notch filter to attenuate at least one blocker signal. The tunable notch filter may include a variable capacitor and an inductor coupled in series between the RF transceiver node and ground. The inductor of the tunable notch filter may include a bondwire coupled between a semiconductor die and a semiconductor package. The inductance may include a physical inductor mounted on the package or a printed circuit board. The tunable notch filter may be enabled by a switch selectively coupling the filter to either the RF transceiver node or ground. The variable capacitor may be digitally programmed with digital values stored in a memory.

    Dynamically reconfigurable frequency selective attenuator for radio frequency receiver front end

    公开(公告)号:US11387857B2

    公开(公告)日:2022-07-12

    申请号:US16998740

    申请日:2020-08-20

    摘要: A wireless device including a receiver circuit coupled to a radio frequency receiver node, a frequency selective attenuator including an inductor and a first capacitor coupled in series to the radio frequency receiver node, and a second capacitor coupled in parallel with the first capacitor. The first capacitor has a first capacitance based on a blocker frequency and the second capacitor has a second capacitance that linearizes the frequency selective attenuator. A method of linearizing a frequency selective attenuator including detecting presence of a blocker signal, activating and programming a capacitor of the frequency selective attenuator to reduce a strength of the blocker signal, determining a frequency difference between the blocker signal and a receive frequency, and coupling a second capacitor to the frequency selective attenuator to linearize the frequency selective attenuator when the frequency difference is no more than an attenuation threshold.

    DYNAMICALLY RECONFIGURABLE FREQUENCY SELECTIVE ATTENUATOR FOR RADIO FREQUENCY RECEIVER FRONT END

    公开(公告)号:US20210175917A1

    公开(公告)日:2021-06-10

    申请号:US16998740

    申请日:2020-08-20

    IPC分类号: H04B1/16 H04B1/18

    摘要: A wireless device including a receiver circuit coupled to a radio frequency receiver node, a frequency selective attenuator including an inductor and a first capacitor coupled in series to the radio frequency receiver node, and a second capacitor coupled in parallel with the first capacitor. The first capacitor has a first capacitance based on a blocker frequency and the second capacitor has a second capacitance that linearizes the frequency selective attenuator. A method of linearizing a frequency selective attenuator including detecting presence of a blocker signal, activating and programming a capacitor of the frequency selective attenuator to reduce a strength of the blocker signal, determining a frequency difference between the blocker signal and a receive frequency, and coupling a second capacitor to the frequency selective attenuator to linearize the frequency selective attenuator when the frequency difference is no more than an attenuation threshold.

    Harmonic Filtering For High Power Radio Frequency (RF) Communications

    公开(公告)号:US20210099148A1

    公开(公告)日:2021-04-01

    申请号:US16586153

    申请日:2019-09-27

    IPC分类号: H03H7/01 H03F3/24

    摘要: Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. For disclosed embodiments, a filter circuit is coupled between a first internal node and a connection pad for an integrated circuit. The filter circuit includes a first inductance, a variable capacitance, and a second inductance. The capacitance amount for the variable capacitance is controlled to tune filtering for the filter circuit to a harmonic of a frequency for a transmit output signal. A power amplifier outputs the transmit output signal to the connection pad without passing through the filter circuit. The filter circuit filters the harmonic of the frequency for the transmit output signal, shunting harmonic current to ground. For one embodiment, the filtered harmonic is a third harmonic of the transmit frequency. For one embodiment, the transmit output signal has an output power greater than or equal to 15 dBm.

    SYSTEM AND METHOD FOR REDUCING OUTPUT HARMONICS

    公开(公告)号:US20190229684A1

    公开(公告)日:2019-07-25

    申请号:US15875274

    申请日:2018-01-19

    摘要: In one form, a signal generator system such as a power amplifier system includes an amplification stage, a lowpass filter, and a controller. The amplification stage includes a first amplifier having an input for receiving an input signal, a control input for receiving a first control signal, and an output. The lowpass filter has a first input coupled to the output of the first amplifier, and an output. The controller has a first input coupled to the output of the lowpass filter, and a first output coupled to the control input of the first amplifier, wherein the controller varies the first control signal to reduce a difference between the output of the lowpass filter and a first target voltage level.

    Multi-Tuner Using Interpolative Dividers
    28.
    发明申请
    Multi-Tuner Using Interpolative Dividers 审中-公开
    多调谐器使用Interpolative Dividers

    公开(公告)号:US20150055021A1

    公开(公告)日:2015-02-26

    申请号:US14505701

    申请日:2014-10-03

    摘要: An apparatus includes a splitter to receive a radio frequency (RF) signal and to provide the RF signal to multiple channels of a tuner. Each channel may include an amplifier to amplify the RF signal, a mixer to downconvert the amplified RF signal to a second frequency signal using a local oscillator (LO) signal, where each of the channels is configured to receive a different LO signal, a filter to filter the downconverted second frequency signal, and a digitizer to digitize the downconverted second frequency signal. A clock generation circuit has multiple interpolative dividers and a frequency synthesizer to generate a reference clock signal. Each of the interpolative dividers is configured to receive the reference clock signal, generate a corresponding LO signal, and provide the corresponding LO signal to the mixer of at least one of the channels.

    摘要翻译: 一种装置包括用于接收射频(RF)信号并将RF信号提供给调谐器的多个信道的分离器。 每个通道可以包括用于放大RF信号的放大器,使用本地振荡器(LO)信号将放大的RF信号下变频到第二频率信号的混频器,其中每个信道被配置为接收不同的LO信号,滤波器 对下变频的第二频率信号进行滤波,以及数字转换器,对下变频的第二频率信号进行数字化。 时钟发生电路具有多个内插分频器和频率合成器,以产生参考时钟信号。 每个内插分频器被配置为接收参考时钟信号,产生相应的LO信号,并将相应的LO信号提供给至少一个信道的混频器。

    Television Tuner To Capture A Cable Spectrum
    29.
    发明申请
    Television Tuner To Capture A Cable Spectrum 有权
    电视调谐器捕获有线频谱

    公开(公告)号:US20140267928A1

    公开(公告)日:2014-09-18

    申请号:US13799351

    申请日:2013-03-13

    IPC分类号: H04N21/426 H04N21/438

    摘要: A method includes receiving a request to tune to a first desired television channel of a cable spectrum provided in a radio frequency (RF) signal received in a multi-tuner circuit configured to receive and process the entire cable spectrum, determining a channel of the channels including the first desired television channel, disabling the channels other than the determined channel, and processing the RF signal in the determined channel.

    摘要翻译: 一种方法包括接收调谐到在配置成接收和处理整个有线频谱的多调谐器电路中接收的射频(RF)信号中提供的电缆频谱的第一期望电视频道的请求,确定频道的频道 包括第一期望的电视频道,禁止除确定的频道以外的频道,以及处理所确定的频道中的RF信号。

    Switching power amplifier with output harmonic suppression

    公开(公告)号:US12047042B2

    公开(公告)日:2024-07-23

    申请号:US17539090

    申请日:2021-11-30

    IPC分类号: H03F3/217 H03L7/081 H03K19/20

    摘要: A switching power amplifier with harmonic suppression including a polyphase converter and a power amplifier stage. The polyphase converter converts a frequency or phase modulated input signal into a 50% duty cycle rail-to-rail signal, a positive 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when high, and a negative 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when low. The power amplifier stage includes first and second branches coupled between upper and lower nodes, each including series-coupled P-channel and N-channel transistors forming an intermediate output node. The transistors of the first branch are controlled by the 50% duty cycle signal, and the transistors of the second branch are controlled by the positive and negative 25% duty cycle signals. The first and second branches generate output currents that are superimposed with each other to suppress third and fifth harmonics.