公开(公告)号：US12047042B2

公开(公告)日：2024-07-23

申请号：US17539090

申请日：2021-11-30

Applicant: Silicon Laboratories Inc.

Inventor： Diptendu Ghosh ,  Mustafa H. Koroglu ,  Dayasagar Gaade ,  Francesco Barale

IPC: H03F3/217 ,  H03L7/081 ,  H03K19/20

CPC classification number: H03F3/217 ,  H03L7/0812 ,  H03F2200/165 ,  H03K19/20

Abstract: A switching power amplifier with harmonic suppression including a polyphase converter and a power amplifier stage. The polyphase converter converts a frequency or phase modulated input signal into a 50% duty cycle rail-to-rail signal, a positive 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when high, and a negative 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when low. The power amplifier stage includes first and second branches coupled between upper and lower nodes, each including series-coupled P-channel and N-channel transistors forming an intermediate output node. The transistors of the first branch are controlled by the 50% duty cycle signal, and the transistors of the second branch are controlled by the positive and negative 25% duty cycle signals. The first and second branches generate output currents that are superimposed with each other to suppress third and fifth harmonics.

公开(公告)号：US20230170855A1

公开(公告)日：2023-06-01

申请号：US17539090

申请日：2021-11-30

Applicant: Silicon Laboratories Inc.

Inventor： Diptendu Ghosh ,  Mustafa H. Koroglu ,  Dayasagar Gaade ,  Francesco Barale

IPC: H03F3/217 ,  H03L7/081

CPC classification number: H03F3/217 ,  H03L7/0812 ,  H03F2200/165 ,  H03K19/20

Abstract: A switching power amplifier with harmonic suppression including a polyphase converter and a power amplifier stage. The polyphase converter converts a frequency or phase modulated input signal into a 50% duty cycle rail-to-rail signal, a positive 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when high, and a negative 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when low. The power amplifier stage includes first and second branches coupled between upper and lower nodes, each including series-coupled P-channel and N-channel transistors forming an intermediate output node. The transistors of the first branch are controlled by the 50% duty cycle signal, and the transistors of the second branch are controlled by the positive and negative 25% duty cycle signals. The first and second branches generate output currents that are superimposed with each other to suppress third and fifth harmonics.