公开(公告)号：US20120299199A1

公开(公告)日：2012-11-29

申请号：US13569562

申请日：2012-08-08

Applicant: Jong Hoon KIM ,  Min Suk SUH ,  Seung Taek YANG ,  Seung Hyun LEE ,  Tae Min KANG

Inventor： Jong Hoon KIM ,  Min Suk SUH ,  Seung Taek YANG ,  Seung Hyun LEE ,  Tae Min KANG

IPC: H01L23/488

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06562 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/83005

Abstract: A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.

公开(公告)号：US20120295376A1

公开(公告)日：2012-11-22

申请号：US13473300

申请日：2012-05-16

Applicant: Keon Jae LEE ,  So Young PARK ,  Seung Hyun LEE ,  Kwi Il PARK ,  Min KOO

Inventor： Keon Jae LEE ,  So Young PARK ,  Seung Hyun LEE ,  Kwi Il PARK ,  Min KOO

IPC: H01L33/30 ,  H01L33/08

CPC classification number: H01L25/0753 ,  A61N5/0622 ,  A61N2005/0652 ,  A61N2005/0662 ,  H01L24/19 ,  H01L33/62 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Disclosed are a method for fabricating a GaN LED array device for optogenetics and a GaN LED array device fabricated thereby.

Abstract translation: 公开了一种用于制造用于光遗传学的GaN LED阵列器件和由其制造的GaN LED阵列器件的方法。

公开(公告)号：US20120241828A1

公开(公告)日：2012-09-27

申请号：US13336069

申请日：2011-12-23

Applicant: Seung Hyun LEE

Inventor： Seung Hyun LEE

IPC: H01L29/82 ,  H01L21/8246

CPC classification number: H01L43/12 ,  G11C11/155 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/5607 ,  H01L27/226 ,  H01L27/228 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08

Abstract: A method for manufacturing a semiconductor memory device includes forming a magnetic tunnel junction layer on a lower electrode, forming a spacer having an annular shape on the magnetic tunnel junction layer, forming upper electrodes on both sidewall surfaces of the annular shaped spacer, removing the spacer, and etching the magnetic tunnel junction layer by using the upper electrodes as an etch mask.

Abstract translation: 一种制造半导体存储器件的方法包括在下电极上形成磁性隧道结层，在磁性隧道结层上形成具有环形形状的间隔物，在环形间隔物的两个侧壁表面上形成上电极， ，并通过使用上电极作为蚀刻掩模蚀刻磁性隧道结层。

公开(公告)号：US20110127611A1

公开(公告)日：2011-06-02

申请号：US12842598

申请日：2010-07-23

Applicant: Seung Hyun LEE

Inventor： Seung Hyun LEE

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor device comprises an active region having an upper portion and a sidewall portion which are protruded from the top surface of a device isolation region, and a silicide film disposed in the upper portion and the sidewall portion of the active region, thereby effectively reducing resistance in a source/drain region of the semiconductor device. As a result, the entire resistance of the semiconductor device comprising a fin-type gate can be reduced to improve characteristics of the semiconductor device.

Abstract translation: 半导体器件包括具有从器件隔离区的顶表面突出的上部和侧壁部分的有源区和设置在有源区的上部和侧壁部分中的硅化物膜，从而有效地降低电阻 在半导体器件的源/漏区中。 结果，可以减少包括鳍型栅极的半导体器件的整个电阻，以改善半导体器件的特性。

公开(公告)号：US20100259657A1

公开(公告)日：2010-10-14

申请号：US12491412

申请日：2009-06-25

Applicant: Seung Hyun LEE ,  Chan Ki HWANG ,  Seung Ho LEE ,  Hee Jin PARK

Inventor： Seung Hyun LEE ,  Chan Ki HWANG ,  Seung Ho LEE ,  Hee Jin PARK

IPC: H04N5/335

CPC classification number: H01L27/14625 ,  H01L24/13 ,  H01L24/16 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14636 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13562 ,  H01L2224/1369 ,  H01L2224/1379 ,  H01L2224/138 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An image sensor module is presented which includes a semiconductor chip, a holder and a coupling member. The semiconductor chip has a semiconductor chip body; an image sensing section over the semiconductor chip body; and bonding pads on the semiconductor chip body. The holder is mounted over the semiconductor chip and has an insulation section over the semiconductor chip body; connection patterns on the insulation section which are electrically coupled to the bonding pads; and a transparent cover over the image sensing section which is connected to the insulation section. The coupling member is interposed between the holder and the semiconductor chip for coupling together the holder to the semiconductor chip.

Abstract translation: 提出了一种图像传感器模块，其包括半导体芯片，保持器和联接构件。 半导体芯片具有半导体芯片体; 半导体芯片本体上的图像感测部分; 以及半导体芯片主体上的接合焊盘。 保持器安装在半导体芯片上，并且在半导体芯片主体上方具有绝缘部分; 绝缘部分上的连接图案，其电耦合到接合焊盘; 以及连接到绝缘部分的图像感测部分上方的透明盖。 联接构件插入在保持器和半导体芯片之间，用于将保持器联接在半导体芯片上。

公开(公告)号：US20090026591A1

公开(公告)日：2009-01-29

申请号：US11854067

申请日：2007-09-12

Applicant: Seung Hyun LEE ,  Seung Taek YANG

Inventor： Seung Hyun LEE ,  Seung Taek YANG

IPC: H01L23/495 ,  H01L21/00

CPC classification number: H01L24/10 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05553 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16105 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  Y10S438/977 ,  H01L2924/00

Abstract: A semiconductor package includes a semiconductor chip provided with a first surface having a bonding pad, a second surface opposing to the first surface and side surfaces; a first redistribution pattern connected with the bonding pad and extending along the first surface from the bonding pad to an end portion of the side surface which meets with the second surface; and a second redistribution pattern disposed over the first redistribution pattern and extending from the side surfaces to the first surface. In an embodiment of the present invention, in which the first redistribution pattern connected with the bonding pad is formed over the semiconductor chip and the second redistribution pattern is formed over the first redistribution pattern, it is capable of reducing a length for signal transfer since the second redistribution pattern is used as an external connection terminal. It is also capable of processing data with high speed, as well as protecting the semiconductor chip having weak brittleness, since the semiconductor package is connected to the substrate without a separate solder ball.

Abstract translation: 半导体封装包括设置有具有接合焊盘的第一表面的半导体芯片，与第一表面相对的第二表面和侧表面; 与所述接合焊盘连接并沿着所述第一表面从所述接合焊盘延伸到与所述第二表面相交的所述侧表面的端部的第一再分布图案; 以及设置在所述第一再分布图案上并且从所述侧表面延伸到所述第一表面的第二再分配图案。 在本发明的一个实施例中，其中与焊盘连接的第一再分布图案形成在半导体芯片之上，并且第二再分配图案形成在第一再分配图案之上，其能够减小用于信号传输的长度，因为 第二再分配模式用作外部连接终端。 由于半导体封装没有单独的焊球而连接到衬底，所以它也能够高速处理数据以及保护具有弱脆性的半导体芯片。