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    SYSTEMS, METHODS, AND APPARATUS FOR PROVIDING POWER TO STORAGE DEVICES
    22.
    发明公开
    SYSTEMS, METHODS, AND APPARATUS FOR PROVIDING POWER TO STORAGE DEVICES 审中-公开

    公开(公告)号：US20240201763A1

    公开(公告)日：2024-06-20

    申请号：US18128194

    申请日：2023-03-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang Hun JUN ,  Yang Seok KI

    IPC: G06F1/26

    CPC classification number: G06F1/266

    Abstract: An apparatus may include a storage structure including a power connection fabric, a first device interface configured to receive a first device having a form that may be compatible with a device form, and connect the first device to the power connection fabric, and a second device interface configured to receive a second device having a form that may be compatible with the device form, and connect the second device to the power connection fabric. The first device may include a storage device, and the second device may include a power device. The first device interface may include a connector to connect the storage device to the power connection fabric. The first device interface may include a device slot to receive the storage device. The second device interface may include a connector to connect the power device to the power connection fabric.

    SYSTEMS AND METHODS FOR A REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) USING A DECODER IN CACHE COHERENT INTERCONNECT STORAGE DEVICES
    25.
    发明公开
    SYSTEMS AND METHODS FOR A REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) USING A DECODER IN CACHE COHERENT INTERCONNECT STORAGE DEVICES 审中-公开

    公开(公告)号：US20230409196A1

    公开(公告)日：2023-12-21

    申请号：US17885520

    申请日：2022-08-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tong ZHANG ,  Heekwon PARK ,  Rekha PITCHUMANI ,  Yang Seok KI

    IPC: G06F3/06

    CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0689

    Abstract: A system is disclosed. The system may include a processor that may issue a byte level protocol request including a byte address. The system may also include a first storage device and a second storage device. The first storage device and the second storage device may support a cache coherent interconnect protocol, the cache coherent interconnect protocol including a block level protocol and a byte level protocol. The first storage device and the second storage device are included in a redundant array of independent disks (RAID). The first storage device may include a first address range, and the second storage device may include a second address range. The second storage device may provide a RAID address range associated with the first address range and the second address range. A decoder associated with the second storage device may be configured to receive the request from the processor. The decoder may determine that the byte address in the RAID address range is associated with a target address range.

    FPGA ACCELERATION SYSTEM FOR MSR CODES
    26.
    发明公开
    FPGA ACCELERATION SYSTEM FOR MSR CODES 审中-公开

    公开(公告)号：US20230367675A1

    公开(公告)日：2023-11-16

    申请号：US18223019

    申请日：2023-07-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mian QIN ,  Joo Hwan LEE ,  Rekha PITCHUMANI ,  Yang Seok KI

    IPC: G06F11/10 ,  G06F13/28

    CPC classification number: G06F11/1076 ,  G06F13/28

    Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.

    STORAGE SYSTEM, METHOD, AND APPARATUS FOR FAST IO ON PCIE DEVICES
    28.
    发明申请
    STORAGE SYSTEM, METHOD, AND APPARATUS FOR FAST IO ON PCIE DEVICES 有权

    公开(公告)号：US20230122094A1

    公开(公告)日：2023-04-20

    申请号：US18084540

    申请日：2022-12-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Heekwon PARK ,  Yang Seok KI

    IPC: G06F13/42 ,  G06F13/28 ,  G06F12/0811

    Abstract: Embodiments of systems and methods for fast input/output (IO) on PCIE devices are described. Such methods include receiving an IO request from a user or application, the IO request comprising instructions for communicating data with a host system, the host system comprising a processing device and a memory device, analyzing information from the IO request in an IO block analyzer to select one of a plurality of communication paths for communicating the data with the host system, defining a routing instruction in a transfer routing information transmitter in response to the selected communication path, communicating the routing instruction in a Transaction Layer Packet (TLP) to an integrated IO (IIO) module of the host system routing the data from the peripheral device to either the processing device or the memory device according to the routing instruction with a data transfer router.

    SYSTEMS, METHODS, AND APPARATUS FOR WEAR-LEVEL AWARE MEMORY ALLOCATION
    29.
    发明申请
    SYSTEMS, METHODS, AND APPARATUS FOR WEAR-LEVEL AWARE MEMORY ALLOCATION 有权

    公开(公告)号：US20220391317A1

    公开(公告)日：2022-12-08

    申请号：US17396550

    申请日：2021-08-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Heekwon PARK ,  Yang Seok KI

    IPC: G06F12/02

    Abstract: A method for memory allocation may include determining an amount of use for a first memory page, wherein the first memory page is mapped to a first page group of a first group level, a second memory page may be mapped to a second page group of the first group level, and the first memory page and the second memory page may be mapped to a third page group of a second group level, and selecting, based on an allocation request, the first memory page based on the amount of use. The amount of use may include a first amount of use, and the method may further include determining a second amount of use for the second memory page, wherein the first memory page may be selected based on the first amount of use and the second amount of use.

    SYSTEMS, METHODS, AND DEVICES FOR FAULT RESILIENT STORAGE
    30.
    发明申请
    SYSTEMS, METHODS, AND DEVICES FOR FAULT RESILIENT STORAGE 有权

    公开(公告)号：US20220291996A1

    公开(公告)日：2022-09-15

    申请号：US17827657

    申请日：2022-05-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yang Seok KI ,  Sungwook RYU ,  Alain TRAN ,  Changho CHOI

    IPC: G06F11/14 ,  G06F3/06 ,  G06F11/10 ,  G06F11/16

    Abstract: A method of operating a storage device may include determining a fault condition of the storage device, selecting a fault resilient mode based on the fault condition of the storage device, and operating the storage device in the selected fault resilient mode. The selected fault resilient mode may include one of a power cycle mode, a reformat mode, a reduced capacity read-only mode, a reduced capacity mode, a reduced performance mode, a read-only mode, a partial read-only mode, a temporary read-only mode, a temporary partial read-only mode, or a vulnerable mode. The storage device may be configured to perform a namespace capacity management command received from the host. The namespace capacity management command may include a resize subcommand and/or a zero-size namespace subcommand. The storage device may report the selected fault resilient mode to a host.

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