SYSTEMS AND METHODS FOR COMPUTATIONAL ACCELERATION

    公开(公告)号:US20240152466A1

    公开(公告)日:2024-05-09

    申请号:US18092925

    申请日:2023-01-03

    CPC classification number: G06F12/109 G06F2212/1041

    Abstract: A system is described. The system may include a host processor, a host memory connected to the host processor, and a storage device connected to the host processor. An accelerator may communicate with the host processor. The accelerator may produce an output. The accelerator may also include a local memory, which may include a first region and a second region. The first region of the local memory of the accelerator may support a first mode, and the second region of the local memory of the accelerator may support a second mode. The accelerator may store the output of the accelerator in a destination, which may include the host memory, the storage device, the first region of the local memory of the accelerator, or the second region of the local memory of the accelerator.

    SYSTEMS, METHODS, AND APPARATUS FOR TRANSFERRING DATA BETWEEN INTERCONNECTED DEVICES

    公开(公告)号:US20230057633A1

    公开(公告)日:2023-02-23

    申请号:US17496759

    申请日:2021-10-07

    Abstract: A method for transferring data may include writing, from a producing device, data to a storage device through an interconnect, determining a consumer device for the data, prefetching the data from the storage device, and transferring, based on the determining, the data to the consumer device through the interconnect. The method may further comprise receiving, at a prefetcher for the storage device, an indication of a relationship between the producing device and the consumer device, and determining the consumer device based on the indication. The method may further comprise placing the data in a stream at the storage device based on the relationship between the producing device and the consumer device. The indication may be provided by an application associated with the consumer device. Receiving the indication may include receiving the indication through a coherent memory protocol for the interconnect.

    SYSTEMS AND METHODS FOR LOAD BALANCING IN A HETEROGENEOUS MEMORY SYSTEM

    公开(公告)号:US20230017824A1

    公开(公告)日:2023-01-19

    申请号:US17511540

    申请日:2021-10-26

    Abstract: A system is disclosed. The system may include a processor and a memory connected to the processor. A first storage device may be connected to the processor. The first storage device may include a first storage portion, which may include a memory page. The first storage portion may extend the memory. A second storage device may also be connected to the processor. The second storage device may also include a second storage portion. The second storage portion may also extend the memory. A load balancing daemon may migrate the memory page from the first storage portion of the first storage device to the second storage portion of the second storage device based at least in part on a first update count of the first storage device and a second update count of the second storage device.

    ENHANCED SSD RELIABILITY
    5.
    发明申请

    公开(公告)号:US20220214836A1

    公开(公告)日:2022-07-07

    申请号:US17701664

    申请日:2022-03-22

    Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include an interface to receive read and write requests from an application on a host. Storage, including at least one chip, may store data. An SSD controller may process the read and write requests from the application. A configuration module may configure the SSD. Storage may include a reliability table which may include entries specifying configurations of the SSD and reliabilities for those configurations.

    AUTOMATIC DATA SEPARATION AND PLACEMENT FOR COMPRESSED DATA IN A STORAGE DEVICE

    公开(公告)号:US20220083231A1

    公开(公告)日:2022-03-17

    申请号:US17120098

    申请日:2020-12-11

    Abstract: A storage device is disclosed. The storage device may include storage for data. A host interface logic may receive a dataset and a logical address from a host. A stream assignment logic may assign a stream identifier (ID) to a compressed dataset based on a compression characteristic of the compressed dataset. The stream ID may be one of at least two stream IDs;
    the compressed dataset may be determined based on the dataset. A logical-to-physical translation layer may map the logical address to a physical address in the storage. A controller may store the compressed dataset at the physical address using the stream ID.

    SYSTEMS, METHODS, AND APPARATUS FOR OPERATING COMPUTATIONAL DEVICES

    公开(公告)号:US20240168819A1

    公开(公告)日:2024-05-23

    申请号:US18121586

    申请日:2023-03-14

    CPC classification number: G06F9/505 G06F9/4881

    Abstract: A method may include performing, at a computational storage device, using first data stored at the computational storage device, a first computational task of a workload, wherein the performing the first computational task of the workload may include generating second data, transferring, from the computational storage device to a computational device, using an interconnect fabric, the second data, and performing, at the computational device, using the second data, a second computational task of the workload. The transferring the second data may include transferring the second data using a root complex of the interconnect fabric. The transferring the second data may include transferring the second data using a switch of the interconnect fabric. The transferring the second data may include performing a peer-to-peer transfer. The transferring the second data may include performing a direct memory access.

    SYSTEM AND METHOD FOR STREAM BASED DATA PLACEMENT ON HYBRID SSD

    公开(公告)号:US20240168646A1

    公开(公告)日:2024-05-23

    申请号:US18426234

    申请日:2024-01-29

    CPC classification number: G06F3/0613 G06F3/0655 G06F3/0679

    Abstract: A multi-stream solid-state device (SSD) includes a normal-access memory associated with a first stream ID, a high-access memory having a higher endurance than the normal-access memory and being associated with a second stream ID, a controller processor, and a processor memory coupled to the controller processor, wherein the processor memory has stored thereon instructions that, when executed by the controller processor, cause the controller processor to perform identifying a data stream ID of an input data stream as one of the first and second stream IDs, in response to identifying the data stream ID as the first stream ID, storing the input data stream in the normal-access memory, and in response to identifying the data stream ID as the second stream ID, storing the input data stream in the high-access memory.

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