公开(公告)号：US20240395313A1

公开(公告)日：2024-11-28

申请号：US18657523

申请日：2024-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Heung Kim ,  Taeyoung Oh

IPC: G11C11/408

Abstract: A memory device includes a bank connected to a plurality of wordlines and a plurality of column select lines (CSLs). Among the plurality of wordlines, every r-th wordline in a column direction may be allocated for metadata where r is a positive integer.

公开(公告)号：US20240221860A1

公开(公告)日：2024-07-04

申请号：US18448346

申请日：2023-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongcheol Kim ,  Taeyoung Oh ,  Hyongryol Hwang

IPC: G11C29/00

CPC classification number: G11C29/76 ,  G11C29/789

Abstract: A semiconductor memory device includes a plurality of memory cells partitioned into a plurality of row blocks that are each associated with at least one respective row block identity bit within a portion of a row address. A row decoder is provided, which includes a repair controller having a plurality of fuse boxes therein that correspond to respective ones of the plurality of row blocks and include a first fuse box configured to store a first defective address. The repair controller is configured to: (i) activate a first redundancy word-line, which replaces a first defective word-line designated by the first defective address, in response to comparing a first access address with the first defective address output from the first fuse box, during a first mode, and (ii) activate a second redundancy word-line, which replaces a first edge word-line designated by the first access address, in response to comparing the first access address with a first reset address output from the first fuse box, during a second mode.

公开(公告)号：US20240038295A1

公开(公告)日：2024-02-01

申请号：US18348591

申请日：2023-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngdo Um ,  Taeyoung Oh ,  Hoseok Seol

IPC: G11C11/4096 ,  H01L25/065 ,  H10B80/00 ,  H01L23/00 ,  G11C11/4076

CPC classification number: G11C11/4096 ,  H01L25/0657 ,  H10B80/00 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  G11C11/4076 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48111 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2224/49109 ,  H01L2224/49112 ,  H01L2924/14361 ,  H01L2224/06135

Abstract: A semiconductor package includes a memory die stack having a clock signal shared by lower and upper bytes. Each of a plurality of memory dies constituting the memory die stack of the semiconductor package includes a first clock circuit configured to generate a read clock signal for a lower byte and an upper byte constituting a data width of the memory die, and a plurality of first die bond pads corresponding to the number of ranks of a memory system including the memory die, and each of the plurality of first die bond pads is set for each rank. The first clock circuit is connected to, among the plurality of first die bond pads, a die bond pad corresponding to a rank to which the memory die belongs.

公开(公告)号：US20240028221A1

公开(公告)日：2024-01-25

申请号：US18302276

申请日：2023-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungho Lee ,  Kiheung Kim ,  Taeyoung Oh ,  Jongcheol Kim ,  Hyongryol Hwang

IPC: G06F3/06

CPC classification number: G06F3/0623 ,  G06F3/0653 ,  G06F3/0673

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows and a row hammer management circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row. The row hammer management circuit includes a hammer address queue. The row hammer management circuit changes the updated count data randomly, based on an event signal indicating a state change of the hammer address queue.

公开(公告)号：US20240012712A1

公开(公告)日：2024-01-11

申请号：US18169769

申请日：2023-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongcheol Kim ,  Hyunsung Shin ,  Hohyun Shin ,  Taeyoung Oh ,  Kyungsoo Ha

IPC: G06F11/10 ,  G06F3/06 ,  G11C11/4096 ,  G11C11/408

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/4096 ,  G11C11/4082

Abstract: A semiconductor memory device includes a memory cell array, a data input/output (I/O) buffer, an I/O gating circuit and a control logic circuit. The memory cell array includes a plurality of sub array blocks arranged in a first direction and a second direction. The data I/O buffer exchanges user data with a memory controller through I/O pads. The I/O gating circuit is connected to the data I/O buffer through data buses and connected to the memory cell array through data I/O lines, and programs mapping relationship between the sub array blocks and the I/O pads, based on a mapping control signal such that uncorrectable errors that are detected by an error correction code engine in the memory controller are reduced. The control logic circuit generates the mapping control signal based on identifier information indicating a type of a central processing unit of the memory controller.

公开(公告)号：US11087822B2

公开(公告)日：2021-08-10

申请号：US17093786

申请日：2020-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjun Shin ,  Su Yeon Doo ,  Taeyoung Oh

IPC: G11C11/00 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  G11C8/18

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

公开(公告)号：US10726882B2

公开(公告)日：2020-07-28

申请号：US16275396

申请日：2019-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su Yeon Doo ,  Taeyoung Oh

IPC: G06F1/00 ,  G11C5/14 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/26 ,  G06F1/3287 ,  G06F1/3296

Abstract: An electronic device includes a memory device including a power switch configured to provide one of a first voltage and a second voltage to an internal circuit in response to a control command. A power management device is configured to generate the first voltage, the second voltage, and the control command and to provide the first voltage, the second voltage, and the control command to the memory device. The power switch provides the second voltage to the internal circuit while a level of the first voltage is changed and provides the first voltage to the internal circuit after a level change of the first voltage is completed.

公开(公告)号：US10255964B2

公开(公告)日：2019-04-09

申请号：US15081071

申请日：2016-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjun Shin ,  Su Yeon Doo ,  Taeyoung Oh

IPC: G11C11/00 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  G11C8/18

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

公开(公告)号：US20250157523A1

公开(公告)日：2025-05-15

申请号：US19024300

申请日：2025-01-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiheung Kim ,  Taeyoung Oh ,  Jongcheol Kim ,  Kyungho Lee ,  Hyongryol Hwang

IPC: G11C11/4078 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit.

公开(公告)号：US12236997B2

公开(公告)日：2025-02-25

申请号：US18357204

申请日：2023-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiheung Kim ,  Taeyoung Oh ,  Jongcheol Kim ,  Kyungho Lee ,  Hyongryol Hwang

IPC: G11C11/4078 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a control logic circuit. The row hammer management circuit stores counted values in count cells of each of the plurality of memory cell rows as count data based on an active command applied to the control logic circuit at a first time point, and performs an internal read-update-write operation to read the count data from the count cells of a target memory cell row from among the plurality of memory cell rows, to update the count data that was read to obtain updated count data, and to write the updated count data in the count cells of the target memory cell row in response to a precharge command applied at a second time point after a first command that is applied to the control logic circuit.