公开(公告)号：US20230342050A1

公开(公告)日：2023-10-26

申请号：US18304813

申请日：2023-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngdo Um ,  Taeyoung Oh ,  Hoseok Seol

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0611 ,  G06F3/0673

Abstract: Provided is a memory system including a host system including a memory controller configured to control a read or write operation for a plurality of memory ranks, based on target or non-target information for the plurality of memory ranks, and a memory device including a storage configured to store on-die termination (ODT) information of the memory ranks. Here, the memory controller is further configured to determine a target rank to be read or written, and transmit information about the determined target rank, to the memory device, and the memory device is further configured to perform a comparison of the ODT information of the memory ranks stored in the storage with target or non-target information received from the memory controller, and change an ODT value of the target rank, based on target information received from the memory controller based on a result of the comparison.

公开(公告)号：US20240038295A1

公开(公告)日：2024-02-01

申请号：US18348591

申请日：2023-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngdo Um ,  Taeyoung Oh ,  Hoseok Seol

IPC: G11C11/4096 ,  H01L25/065 ,  H10B80/00 ,  H01L23/00 ,  G11C11/4076

CPC classification number: G11C11/4096 ,  H01L25/0657 ,  H10B80/00 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  G11C11/4076 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48111 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4903 ,  H01L2224/49109 ,  H01L2224/49112 ,  H01L2924/14361 ,  H01L2224/06135

Abstract: A semiconductor package includes a memory die stack having a clock signal shared by lower and upper bytes. Each of a plurality of memory dies constituting the memory die stack of the semiconductor package includes a first clock circuit configured to generate a read clock signal for a lower byte and an upper byte constituting a data width of the memory die, and a plurality of first die bond pads corresponding to the number of ranks of a memory system including the memory die, and each of the plurality of first die bond pads is set for each rank. The first clock circuit is connected to, among the plurality of first die bond pads, a die bond pad corresponding to a rank to which the memory die belongs.

公开(公告)号：US20250149077A1

公开(公告)日：2025-05-08

申请号：US18937774

申请日：2024-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Yoon ,  Jaemin Choi ,  ChangSik Yoo ,  Ki-Heung Kim ,  Hoseok Seol ,  Youngdo Um ,  Hyongryol Hwang

IPC: G11C8/18 ,  G11C8/06 ,  H03K19/173 ,  H03K21/08

Abstract: An input/output interface circuit includes a common receiving driver configured to receive a differential clock signal and output a first clock signal corresponding to the differential clock signal and a pair of sub-channels connected to the common receiving driver. Each sub-channel of the pair of sub-channels may be configured to receive the first clock signal and a chip select signal, output a second clock signal through a logical AND operation of the first clock signal and the chip select signal, and output a single clock signal, among the second clock signal and one or more divided clock signals. The single clock signal is used to sample a command address signal.