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    PROCESSOR AND MEMORY CONTROL METHOD
    21.
    发明申请
    PROCESSOR AND MEMORY CONTROL METHOD 审中-公开
    处理器和存储器控制方法

    公开(公告)号：US20160196206A1

    公开(公告)日：2016-07-07

    申请号：US14909443

    申请日：2014-07-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byoungik Kang ,  Jinyoung Park ,  Seungwook Lee ,  Eunseok Hong

    IPC: G06F12/02 ,  G06F13/16 ,  G06F13/18

    CPC classification number: G06F12/023 ,  G06F12/0888 ,  G06F13/1663 ,  G06F13/1694 ,  G06F13/18 ,  G06F2212/1016 ,  G06F2212/1044 ,  Y02D10/13 ,  Y02D10/14

    Abstract: The present invention relates to a processor and a memory. More specifically, the present invention relates to a switchable on chip memory accessible by various master intellectual properties (IPs) and a method for controlling the same, and the method for controlling the on chip memory, according to one embodiment of the present invention, can comprise the steps of: setting memory allocation information including at least one among modes of respective master IPs, priority, space size of a required memory, and correlation with other master IPs; and allocating memories for the respective master IPs by using the memory allocation information. According to the one embodiment of the present invention, various master IPs within an embedded SoC are capable of utilizing all of the advantages of an on chip buffer and an on chip cache.

    Abstract translation: 本发明涉及处理器和存储器。 更具体地，本发明涉及可通过各种主要知识产权（IP）访问的可切换片上存储器及其控制方法，并且根据本发明的一个实施例的用于控制片上存储器的方法可以 包括以下步骤：设置包括各个主IP的模式，优先级，所需存储器的空间大小以及与其他主IP的相关性中的至少一个的存储器分配信息; 以及通过使用存储器分配信息为各个主IP分配存储器。 根据本发明的一个实施例，嵌入式SoC内的各种主IP能够利用片上缓冲器和片上高速缓存的所有优点。

    Method for layout design and semiconductor device manufactured based on the same
    22.
    发明授权
    Method for layout design and semiconductor device manufactured based on the same 有权

    公开(公告)号：US11010533B2

    公开(公告)日：2021-05-18

    申请号：US16996044

    申请日：2020-08-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinyoung Park

    IPC: G06F30/398 ,  G06F30/392 ,  G06F119/18

    Abstract: Disclosed is a computer-readable medium including a program code. The program code, when executed by a processor, causes the processor to place an electrically active pattern having a first width and a first least margin area, on a layer, to place a first dummy pattern having a second width wider than the first width and having a second least margin area, on the layer, and to place a second dummy pattern having a third width and a third least margin area, on the layer, based on whether a ratio of an area of the layer to areas of the electrically active pattern and the first dummy pattern is within a reference range.

    Electronic device and method for controlling audio path thereof
    23.
    发明授权
    Electronic device and method for controlling audio path thereof 有权

    公开(公告)号：US10963211B2

    公开(公告)日：2021-03-30

    申请号：US15938005

    申请日：2018-03-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinyoung Park ,  Chan-Yong Jung ,  Ga-Jin Song ,  Dong-Ho Jang

    IPC: G06F17/00 ,  G06F3/16 ,  G06F3/0481 ,  G06F3/0484 ,  G06F3/0482 ,  G06F3/0488 ,  G06F3/14

    Abstract: Various embodiments of the present disclosure relate to an electronic device. The electronic device includes a housing, a touch screen display disposed on a surface of the housing, at least one wireless or wired communication circuit located inside the housing, a speaker exposed through the housing, at least one processor positioned inside the housing and operatively connected to the display, the communication circuit, and the speaker and a memory positioned inside the housing and operatively connected to the processor, wherein the memory stores instructions that, when executed, cause the at least one processor to detect that the electronic device is communicating with an external display device through the communication circuit, provide first data for rendering a first user interface on the external display device through the communication circuit responsive detecting that the electronic device is communicating with the external display device, determine whether the external display device can output audio data, in response that the external device can output audio data, provide second data configured to render a second user interface on the external display device through the communication circuit, wherein the second user interface allows a user to select one of the electronic device and the external display device for providing audio generated from or relayed through the electronic device, receive a selection of one of the electronic device and the external display device through the communication circuit or the touch screen display, and adapt an audio output path of the electronic device to provide the audio on the basis of the selection responsive to receiving the selection.

    System for fabricating a semiconductor device
    25.
    发明授权
    System for fabricating a semiconductor device 有权

    公开(公告)号：US10892142B2

    公开(公告)日：2021-01-12

    申请号：US16182737

    申请日：2018-11-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangjean Jeon ,  Jinyoung Park ,  Chanhoon Park ,  Hoyong Park ,  Jin Young Bang ,  JungHwan Um ,  Il Sup Choi ,  Je-Woo Han

    IPC: H01J37/32 ,  H01L21/683

    Abstract: A system for fabricating a semiconductor device may include a chamber, an electrostatic chuck used to load a substrate, a power source supplying an RF power to the electrostatic chuck, an impedance matcher between the power source and the electrostatic chuck, and a power transmission unit connecting the electrostatic chuck to the impedance matcher. The power transmission unit may include a power rod, which is connected to the electrostatic chuck and has a first outer diameter, and a coaxial cable. The coaxial cable may include an inner wire, an outer wire, and a dielectric material between the outer and inner wires. The inner wire connects the power rod to the impedance matcher and has a second outer diameter less than the first outer diameter. The outer wire is connected to the chamber and is provided to enclose the inner wire and has a first inner diameter less than the first outer diameter and greater than the second outer diameter. A ratio of the first inner diameter to the second outer diameter is greater than a dielectric constant of the dielectric material and less than three times the dielectric constant of the dielectric material.

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