公开(公告)号：US11126712B2

公开(公告)日：2021-09-21

申请号：US15775519

申请日：2016-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungik Kang ,  Minsoo Kim ,  Wonjin Kim ,  Philkoo Yeo ,  Sangchul Jung ,  Taedong Jung

IPC: G06F11/00 ,  G06F12/14 ,  G06F12/16 ,  G08B23/00 ,  G06F21/55 ,  H04L29/06 ,  G06F21/70 ,  G06F21/56

Abstract: A method for operating an apparatus according to various embodiments may comprise the operations of: detecting whether a first signal transmitted from a control device to a storage device includes a designated address; and transmitting a second signal to the control device if the first signal includes the designated address, wherein the first signal may be a signal for transmitting, by the control device, a request for data to the storage device, and the second signal may be a signal for detecting whether uncommon data is included in a signal generated from the first signal.

公开(公告)号：US10895987B2

公开(公告)日：2021-01-19

申请号：US16018790

申请日：2018-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungik Kang ,  Jinyoung Park ,  Heesub Shin ,  Seungwook Lee

IPC: G06F3/06 ,  G06F12/02

Abstract: Disclosed are a memory compression method of an electronic device and an apparatus thereof. The method for compressing memory in an electronic device may include: detecting a request for executing the first application; determining whether or not the memory compression is required for the execution of the first application; when the memory compression is required, compressing the memory corresponding to an application in progress in the background of the electronic device; and executing the first application.

公开(公告)号：US10193905B2

公开(公告)日：2019-01-29

申请号：US15255469

申请日：2016-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungik Kang ,  Minsoo Kim ,  Wonjin Kim ,  Philkoo Yeo ,  Sangchul Jung ,  Taedong Jung

IPC: G06F11/00 ,  H04L29/06 ,  G06F12/0813 ,  H04L12/851 ,  H04W84/10 ,  H04W84/12

Abstract: An apparatus and a method for processing data are provided. The method for processing data by a terminal. The method includes identifying a plurality of inspection types for a packet; determining at least one inspection type from the plurality of inspection types for the packet based on a predetermined criterion; and processing the determined at least one inspection type for the packet.

公开(公告)号：US10037143B2

公开(公告)日：2018-07-31

申请号：US14436344

申请日：2014-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungik Kang ,  Jinyoung Park ,  Heesub Shin ,  Seungwook Lee

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0608 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/023 ,  G06F2212/401

Abstract: Disclosed are a memory compression method of an electronic device and an apparatus thereof. The method for compressing memory in an electronic device may include: detecting a request for executing the first application; determining whether or not the memory compression is required for the execution of the first application; when the memory compression is required, compressing the memory corresponding to an application in progress in the background of the electronic device; and executing the first application.

公开(公告)号：US20160196206A1

公开(公告)日：2016-07-07

申请号：US14909443

申请日：2014-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungik Kang ,  Jinyoung Park ,  Seungwook Lee ,  Eunseok Hong

IPC: G06F12/02 ,  G06F13/16 ,  G06F13/18

CPC classification number: G06F12/023 ,  G06F12/0888 ,  G06F13/1663 ,  G06F13/1694 ,  G06F13/18 ,  G06F2212/1016 ,  G06F2212/1044 ,  Y02D10/13 ,  Y02D10/14

Abstract: The present invention relates to a processor and a memory. More specifically, the present invention relates to a switchable on chip memory accessible by various master intellectual properties (IPs) and a method for controlling the same, and the method for controlling the on chip memory, according to one embodiment of the present invention, can comprise the steps of: setting memory allocation information including at least one among modes of respective master IPs, priority, space size of a required memory, and correlation with other master IPs; and allocating memories for the respective master IPs by using the memory allocation information. According to the one embodiment of the present invention, various master IPs within an embedded SoC are capable of utilizing all of the advantages of an on chip buffer and an on chip cache.

Abstract translation: 本发明涉及处理器和存储器。 更具体地，本发明涉及可通过各种主要知识产权（IP）访问的可切换片上存储器及其控制方法，并且根据本发明的一个实施例的用于控制片上存储器的方法可以 包括以下步骤：设置包括各个主IP的模式，优先级，所需存储器的空间大小以及与其他主IP的相关性中的至少一个的存储器分配信息; 以及通过使用存储器分配信息为各个主IP分配存储器。 根据本发明的一个实施例，嵌入式SoC内的各种主IP能够利用片上缓冲器和片上高速缓存的所有优点。