Neural network accelerator
    21.
    发明授权

    公开(公告)号:US11954582B2

    公开(公告)日:2024-04-09

    申请号:US18085939

    申请日:2022-12-21

    CPC classification number: G06N3/063 G06F7/485 G06F7/523

    Abstract: Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number of digits of the addition result depending on a shift value to generate a shifted addition result, and an accumulator generating output feature data based on the shifted addition result.

    Time-delayed convolutions for neural network device and method

    公开(公告)号:US11521046B2

    公开(公告)日:2022-12-06

    申请号:US16170081

    申请日:2018-10-25

    Abstract: A method of performing operations on a plurality of inputs and a same kernel using a delay time by using a same processor, and a neural network device thereof are provided, the neural network device includes input data including a first input and a second input, and a processor configured to obtain a first result by performing operations between the first input and a plurality of kernels, to obtain a second result by performing operations between the second input, which is received at a time delayed by a first interval from a time when the first input is received, and the plurality of kernels, and to obtain output data using the first result and the second result. The neural network device may include neuromorphic hardware and may perform convolutional neural network (CNN) mapping.

    SEMICONDUCTOR DEVICE
    30.
    发明公开

    公开(公告)号:US20240321940A1

    公开(公告)日:2024-09-26

    申请号:US18423647

    申请日:2024-01-26

    CPC classification number: H01L28/60

    Abstract: A semiconductor device including a substrate and a capacitor structure arranged on the substrate. The capacitor structure includes a plurality of lower electrodes extending in a vertical direction perpendicular to a surface of the substrate and spaced apart from each other, supporters arranged between the plurality of lower electrodes, an upper electrode spaced apart from each of the plurality of lower electrodes, a dielectric layer arranged between each of the lower electrodes and the upper electrode, and a plurality of particles each in contact with the dielectric layer and arranged between each of the plurality of lower electrodes and the upper electrode.

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