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公开(公告)号：US11694067B2
公开(公告)日：2023-07-04
申请号：US16451586
申请日：2019-06-25
发明人： Jae-Joon Kim , Jinseok Kim , Taesu Kim
摘要： An operating method of a neuromorphic processor which processes data based on a neural network including a first layer including axons and a second layer including neurons includes receiving synaptic weights between the first layer and the second layer, decomposing the synaptic weights into presynaptic weights, a number of which is identical to a number of the axons, and postsynaptic weights, a number of which is identical to a number of the synaptic weights, and storing the presynaptic weights and the postsynaptic weights. A precision of each of the synaptic weights is a first number of bits, a precision of each of the presynaptic weights is a second number of bits, and a precision of each of the postsynaptic weights is a third number of bits. The third number of the bits is smaller than the first number of the bits.
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公开(公告)号：US11681899B2
公开(公告)日：2023-06-20
申请号：US16561378
申请日：2019-09-05
发明人： Sungho Kim , Yulhwa Kim , Hyungjun Kim , Jae-Joon Kim , Jinseok Kim
摘要： A method of implementing a neural network in a neuromorphic apparatus having a memory and processing circuitry, where the method includes dividing, by the processing circuitry, the neural network into a plurality of sub-networks based on a size of a core of the memory to implement the neural network, initializing, by the processing circuitry, a hyper-parameter used in the sub-networks, and training, by the processing circuitry, the sub-networks by using the hyper-parameter.
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公开(公告)号：US11954582B2
公开(公告)日：2024-04-09
申请号：US18085939
申请日：2022-12-21
发明人： Sungju Ryu , Hyungjun Kim , Jae-Joon Kim
摘要： Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number of digits of the addition result depending on a shift value to generate a shifted addition result, and an accumulator generating output feature data based on the shifted addition result.
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公开(公告)号：US12093341B2
公开(公告)日：2024-09-17
申请号：US17137803
申请日：2020-12-30
发明人： Jaeha Kung , Jae-Joon Kim , Junki Park
摘要： A matrix data processing method performed by a computing device which performs a matrix multiplication operation includes, with respect to each of one or more elements included in a matrix, when a value of each element satisfies a designated condition, determining the element to be a don't-care element and determining an output value of the don't-care element, generating a bitstream based on the output value of the don't-care element and index values of valid elements included in the matrix, and equally dividing the bitstream into pieces of a designated number, and generating a Huffman code corresponding to each of a plurality of lower bitstreams that are generated as a result of the equal division.
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公开(公告)号：US12125524B2
公开(公告)日：2024-10-22
申请号：US18303309
申请日：2023-04-19
发明人： Jinseok Kim , Yulhwa Kim , Jae-Joon Kim , Hyungjun Kim
IPC分类号： G11C11/412 , G06N3/08 , G11C11/418 , G11C11/419
CPC分类号： G11C11/412 , G06N3/08 , G11C11/418 , G11C11/419
摘要： Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.
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公开(公告)号：US11790985B2
公开(公告)日：2023-10-17
申请号：US17723358
申请日：2022-04-18
发明人： Jinseok Kim , Yulhwa Kim , Jae-Joon Kim , Hyungjun Kim
IPC分类号： G11C11/412 , G11C11/418 , G11C11/419 , G06N3/08
CPC分类号： G11C11/412 , G06N3/08 , G11C11/418 , G11C11/419
摘要： Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.
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公开(公告)号：US11755897B2
公开(公告)日：2023-09-12
申请号：US18094351
申请日：2023-01-07
发明人： Jae-Joon Kim , Hyungjun Kim , Yulhwa Kim
CPC分类号： G06N3/063 , G06N3/04 , G11C11/54 , G11C13/004 , G11C13/0069
摘要： Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.
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公开(公告)号：US11580368B2
公开(公告)日：2023-02-14
申请号：US16687599
申请日：2019-11-18
发明人： Jae-Joon Kim , Hyungjun Kim , Yulhwa Kim
摘要： Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.
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公开(公告)号：US11562218B2
公开(公告)日：2023-01-24
申请号：US16868845
申请日：2020-05-07
发明人： Sungju Ryu , Hyungjun Kim , Jae-Joon Kim
摘要： Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number of digits of the addition result depending on a shift value to generate a shifted addition result, and an accumulator generating output feature data based on the shifted addition result.
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公开(公告)号：US11556765B2
公开(公告)日：2023-01-17
申请号：US16454881
申请日：2019-06-27
发明人： Jae-Joon Kim , Jinseok Kim , Taesu Kim
摘要： A neuromorphic system includes an address translation device that translates an address corresponding to each of synaptic weights between presynaptic neurons and postsynaptic neurons to generate a translation address, and a plurality of synapse memories that store the synaptic weights based on the translation address. The translation address is generated such that at least two of synaptic weights corresponding to each of the postsynaptic neurons are stored in different synapse memories of the plurality of synapse memories and such that at least two of synaptic weights corresponding to each of the presynaptic neurons are stored in different synapse memories.
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