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公开(公告)号：US11521046B2
公开(公告)日：2022-12-06
申请号：US16170081
申请日：2018-10-25
发明人： Sungho Kim , Jinseok Kim , Yulhwa Kim , Jaejoon Kim , Dusik Park , Hyungjun Kim
摘要： A method of performing operations on a plurality of inputs and a same kernel using a delay time by using a same processor, and a neural network device thereof are provided, the neural network device includes input data including a first input and a second input, and a processor configured to obtain a first result by performing operations between the first input and a plurality of kernels, to obtain a second result by performing operations between the second input, which is received at a time delayed by a first interval from a time when the first input is received, and the plurality of kernels, and to obtain output data using the first result and the second result. The neural network device may include neuromorphic hardware and may perform convolutional neural network (CNN) mapping.
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公开(公告)号：US11681899B2
公开(公告)日：2023-06-20
申请号：US16561378
申请日：2019-09-05
发明人： Sungho Kim , Yulhwa Kim , Hyungjun Kim , Jae-Joon Kim , Jinseok Kim
摘要： A method of implementing a neural network in a neuromorphic apparatus having a memory and processing circuitry, where the method includes dividing, by the processing circuitry, the neural network into a plurality of sub-networks based on a size of a core of the memory to implement the neural network, initializing, by the processing circuitry, a hyper-parameter used in the sub-networks, and training, by the processing circuitry, the sub-networks by using the hyper-parameter.
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公开(公告)号：US12125524B2
公开(公告)日：2024-10-22
申请号：US18303309
申请日：2023-04-19
发明人： Jinseok Kim , Yulhwa Kim , Jae-Joon Kim , Hyungjun Kim
IPC分类号： G11C11/412 , G06N3/08 , G11C11/418 , G11C11/419
CPC分类号： G11C11/412 , G06N3/08 , G11C11/418 , G11C11/419
摘要： Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.
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公开(公告)号：US11790985B2
公开(公告)日：2023-10-17
申请号：US17723358
申请日：2022-04-18
发明人： Jinseok Kim , Yulhwa Kim , Jae-Joon Kim , Hyungjun Kim
IPC分类号： G11C11/412 , G11C11/418 , G11C11/419 , G06N3/08
CPC分类号： G11C11/412 , G06N3/08 , G11C11/418 , G11C11/419
摘要： Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.
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公开(公告)号：US11755897B2
公开(公告)日：2023-09-12
申请号：US18094351
申请日：2023-01-07
发明人： Jae-Joon Kim , Hyungjun Kim , Yulhwa Kim
CPC分类号： G06N3/063 , G06N3/04 , G11C11/54 , G11C13/004 , G11C13/0069
摘要： Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.
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公开(公告)号：US11580368B2
公开(公告)日：2023-02-14
申请号：US16687599
申请日：2019-11-18
发明人： Jae-Joon Kim , Hyungjun Kim , Yulhwa Kim
摘要： Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.
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