知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

54 records (took 0.021 seconds)

    Display device and manufacturing method thereof
    21.
    发明授权
    Display device and manufacturing method thereof 有权

    公开(公告)号：US11101336B2

    公开(公告)日：2021-08-24

    申请号：US16260293

    申请日：2019-01-29

    Applicant: SAMSUNG DISPLAY CO., LTD.

    Inventor： Yu-Gwang Jeong ,  Su Bin Bae ,  Joon Geol Lee ,  Sang Gab Kim ,  Shin Il Choi

    IPC: H01L29/08 ,  H01L27/32 ,  H01L29/786 ,  H01L29/45 ,  H01L29/417 ,  H01L27/12

    Abstract: A display device and a method for manufacturing a display device, the device including a semiconductor layer on a substrate; a gate insulation layer and an interlayer insulation layer that overlap the semiconductor layer; contact holes that penetrate the gate insulation layer and the interlayer insulation layer; a source electrode and a drain electrode that are electrically connected with the semiconductor layer through the contact holes; a light emitting diode that is connected with the drain electrode; and first spacers and second spacers between the source electrode and the interlayer insulation layer and between the drain electrode and the interlayer insulation layer in the contact holes.

    Method of fabricating display device
    23.
    发明授权
    Method of fabricating display device 有权

    公开(公告)号：US09711545B2

    公开(公告)日：2017-07-18

    申请号：US15262943

    申请日：2016-09-12

    Applicant: Samsung Display Co. Ltd.

    Inventor： Ji Young Park ,  Dong Il Kim ,  Sang Gab Kim

    IPC: H01L27/12 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368

    CPC classification number: H01L27/1288 ,  G02F1/133345 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2201/121 ,  G02F2201/123 ,  H01L27/124

    Abstract: A method of fabricating a display device includes forming a thin-film transistor including a gate electrode, a source electrode and a drain electrode on a substrate, forming a first insulating layer and a second insulating layer on the thin-film transistor, forming a common electrode on the second insulating layer by depositing a common electrode material on the second insulating layer, plasma-treating a photoresist pattern on the common electrode material, and etching the common electrode material using the plasma-treated photoresist pattern as a mask, defining a contact hole in the second insulating layer which corresponds to the drain electrode using the plasma-treated photoresist pattern and the common electrode as a mask, forming a third insulating layer on the second insulating layer and the common electrode to expose the contact hole and the drain electrode and forming a pixel electrode connected to the drain electrode on the third insulating layer.

    Thin film transistor array panel and manufacturing method thereof
    24.
    发明授权
    Thin film transistor array panel and manufacturing method thereof 有权
    薄膜晶体管阵列面板及其制造方法

    公开(公告)号：US09041001B2

    公开(公告)日：2015-05-26

    申请号：US14151658

    申请日：2014-01-09

    Applicant: SAMSUNG DISPLAY CO., LTD.

    Inventor： Pil Soon Hong ,  Gwui-Hyun Park ,  Jin-Su Byun ,  Sang Gab Kim

    IPC: H01L27/12 ,  H01L29/417

    CPC classification number: H01L27/124 ,  H01L29/41733

    Abstract: The present invention relates to a thin film transistor array panel and a manufacturing method thereof that prevent disconnection of wiring due to misalignment of a mask, and simplify a process and reduce cost by reducing the number of masks. The thin film transistor array panel according to the disclosure includes a source electrode enclosing an outer part of the first contact hole and formed on the second insulating layer; a drain electrode enclosing an outer part of the second contact hole and formed on the second insulating layer; a first connection electrode connecting the source region of the semiconductor layer and the source electrode through the first contact hole; and a second connection electrode connecting the drain region of the semiconductor layer and the drain electrode through the second contact hole.

    Abstract translation: 薄膜晶体管阵列面板及其制造方法技术领域本发明涉及一种薄膜晶体管阵列面板及其制造方法，其能够防止由于掩模的未对准而使布线断开，并且通过减少掩模数来简化处理并降低成本。 根据本发明的薄膜晶体管阵列面板包括：源电极，其包围第一接触孔的外部部分并形成在第二绝缘层上; 漏电极，其包围所述第二接触孔的外部部分并形成在所述第二绝缘层上; 第一连接电极，通过第一接触孔连接半导体层的源极区域和源极电极; 以及通过第二接触孔连接半导体层的漏极区域和漏极电极的第二连接电极。

    Thin film transistor array panel
    25.
    发明授权
    Thin film transistor array panel 有权
    薄膜晶体管阵列面板

    公开(公告)号：US09006742B2

    公开(公告)日：2015-04-14

    申请号：US13952059

    申请日：2013-07-26

    Applicant: Samsung Display Co., Ltd.

    Inventor： Jeong Min Park ,  Dong-Won Woo ,  Je Hyeong Park ,  Sang Gab Kim ,  Jung-Soo Lee ,  Ji-Hyun Kim

    IPC: H01L29/786 ,  H01L27/12

    CPC classification number: H01L29/786 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/78645

    Abstract: A manufacturing method of a thin film transistor array panel includes: simultaneously forming a gate conductor and a first electrode on a substrate, using a non-peroxide-based etchant; forming a gate insulating layer on the gate conductor and the first electrode; forming a semiconductor, a source electrode, and a drain electrode on the gate insulating layer; forming a passivation layer on the semiconductor, the source electrode, and the drain electrode; and forming a second electrode layer on the passivation layer.

    Abstract translation: 薄膜晶体管阵列板的制造方法包括：使用非过氧化物的蚀刻剂，在基板上同时形成栅极导体和第一电极; 在所述栅极导体和所述第一电极上形成栅极绝缘层; 在栅极绝缘层上形成半导体，源电极和漏电极; 在半导体，源电极和漏电极上形成钝化层; 以及在所述钝化层上形成第二电极层。

    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
    26.
    发明申请
    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 有权
    薄膜晶体管阵列及其制造方法

    公开(公告)号：US20140117361A1

    公开(公告)日：2014-05-01

    申请号：US13830269

    申请日：2013-03-14

    Applicant: Samsung Display Co., Ltd.

    Inventor： Ji-Young Park ,  Yu-Gwang Jeong ,  Sang Gab Kim ,  Joon Geol Lee

    IPC: H01L29/786 ,  H01L29/66

    CPC classification number: H01L27/1259 ,  G02F1/134363 ,  G02F1/136227 ,  H01L27/124 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678

    Abstract: A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side.

    Abstract translation: 薄膜晶体管阵列面板包括基板，栅极线，每个栅极线包括栅极焊盘，栅极绝缘层，数据线，每条数据线包括连接到源极和漏极的数据焊盘，设置在数据线上的第一钝化层和 漏电极，第一电场产生电极，设置在第一电场产生电极上的第二钝化层和第二电场产生电极。 栅极绝缘层和第一和第二钝化层包括暴露栅极焊盘的一部分的第一接触孔，第一和第二钝化层包括暴露数据焊盘的一部分的第二接触孔，以及第一和第二钝化层中的至少一个 并且第二接触孔具有在上侧具有比在下侧更宽的面积的正锥形结构。

Patent Agency Ranking