公开(公告)号：US11935849B2

公开(公告)日：2024-03-19

申请号：US18061763

申请日：2022-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Sangkyu Lee ,  Yongkoon Lee

IPC: H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01Q1/22 ,  H01Q1/52 ,  H01Q21/06

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01Q1/2283 ,  H01Q1/523 ,  H01Q1/526 ,  H01L2223/6677 ,  H01L2224/214 ,  H01L2924/19106 ,  H01L2924/3025 ,  H01Q21/065

Abstract: A semiconductor package includes a front redistribution structure having a first surface and a second surface, opposite to the first surface, a dielectric layer, an antenna substrate including a plurality of antenna members in the dielectric layer, a semiconductor chip having a connection pad connected to the plurality of antenna members, a conductive core structure having a first through-hole accommodating the antenna substrate and a second through-hole accommodating the semiconductor chip, and a rear redistribution structure including a conductive cover layer exposing an upper portion of the antenna substrate and covering an upper portion of the semiconductor chip, and a conductive via connecting the conductive cover layer to the conductive core structure.

公开(公告)号：US11842950B2

公开(公告)日：2023-12-12

申请号：US17685227

申请日：2022-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongjin Park ,  Myungsam Kang ,  Younggwan Ko

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L23/49534 ,  H01L23/3157 ,  H01L23/49531 ,  H01L23/49537 ,  H01L23/5226 ,  H01L24/09 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02379

Abstract: A package module includes a connection structure including one or more redistribution layers, a semiconductor chip disposed on the connection structure and having a connection pad electrically connected to the one or more redistribution layers, a plurality of electronic components disposed on the connection structure and electrically connected to the one or more redistribution layers, one or more frames disposed on the connection structure, and an encapsulant disposed on the connection structure, and respectively covering at least portions of the semiconductor chip, the plurality of electronic components, and the one or more frames. At least a portion of an outer side surface of the encapsulant is coplanar on the same level as at least a portion of an outer side surface of at least one of the one or more frames.

公开(公告)号：US20230096506A1

公开(公告)日：2023-03-30

申请号：US18061763

申请日：2022-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Sangkyu Lee ,  Yongkoon Lee

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/22 ,  H01Q1/52 ,  H01L23/31

Abstract: A semiconductor package includes a front redistribution structure having a first surface and a second surface, opposite to the first surface, a dielectric layer, an antenna substrate including a plurality of antenna members in the dielectric layer, a semiconductor chip having a connection pad connected to the plurality of antenna members, a conductive core structure having a first through-hole accommodating the antenna substrate and a second through-hole accommodating the semiconductor chip, and a rear redistribution structure including a conductive cover layer exposing an upper portion of the antenna substrate and covering an upper portion of the semiconductor chip, and a conductive via connecting the conductive cover layer to the conductive core structure.

公开(公告)号：US11581284B2

公开(公告)日：2023-02-14

申请号：US17203372

申请日：2021-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Kyungdon Mun

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/522

Abstract: A semiconductor package includes a redistribution structure including an insulating layer and a redistribution layer on the insulating layer, and having a first surface and a second surface opposing the first surface, and an under-bump metal (UBM) structure including an UBM pad protruding from the first surface of the redistribution structure, and an UBM via penetrating through the insulating layer and connecting the redistribution layer and the UBM pad. A lower surface of the UBM via has a first area in contact with the UBM pad, and a second area having a step configuration relative to the first area and that extends outwardly of the first area.

公开(公告)号：US11569158B2

公开(公告)日：2023-01-31

申请号：US17228784

申请日：2021-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Kyung Don Mun ,  Bongju Cho

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31

Abstract: A semiconductor package includes a redistribution substrate having a dielectric layer and a wiring pattern in the dielectric layer, the wiring pattern including a line part that extends horizontally, and a via part connected to the line part, the via part having a width less than a width of the line part, a passivation layer on a top surface of the redistribution substrate, the passivation layer including a material different from a material of the dielectric layer, a conductive pillar that penetrates the passivation layer, the conductive pillar being connected to the via part, and a connection terminal on a top surface of the conductive pillar, a distance between the top surface of the conductive pillar and a top surface of the passivation layer being greater than a thickness of the passivation layer.

公开(公告)号：US11538737B2

公开(公告)日：2022-12-27

申请号：US17012294

申请日：2020-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Kyungdon Mun

IPC: H01L23/485 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes a redistribution substrate having a first redistribution layer, a semiconductor chip on the redistribution substrate and connected to the first redistribution layer, a vertical connection conductor on the redistribution substrate and electrically connected to the semiconductor chip through the first redistribution layer, a core member having a first through-hole accommodating the semiconductor chip and a second through-hole accommodating the vertical connection conductor, and an encapsulant covering at least a portion of each of the semiconductor chip, the vertical connection conductor, and the core member, the encapsulant filling the first and second through-holes, wherein the vertical connection conductor has a cross-sectional shape with a side surface tapered to have a width of a lower surface thereof is narrower than a width of an upper surface thereof, and the first and second through-holes have a cross-sectional shape tapered in a direction opposite to the vertical connection conductor.

公开(公告)号：US20240321728A1

公开(公告)日：2024-09-26

申请号：US18733705

申请日：2024-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Bongju Cho

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/28 ,  H01L23/31 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/528 ,  H01L23/53238 ,  H01L24/14

Abstract: A semiconductor package includes: a first redistribution structure having a first surface and a second surface opposing the first surface, and including a first insulating layer and a first redistribution layer disposed on the first insulating layer; a semiconductor chip disposed on the first surface of the first redistribution structure, and including a connection pad electrically connected to the first redistribution layer and embedded in the first insulating layer; a vertical connection structure disposed on the first surface and electrically connected to the first redistribution layer; an encapsulant encapsulating at least a portion of each of the semiconductor chip and the vertical connection structure; a second redistribution structure disposed on the encapsulant and including a second redistribution layer electrically connected to the vertical connection structure; and a connection bump disposed on the second surface and electrically connected to the first redistribution layer.

公开(公告)号：US12021020B2

公开(公告)日：2024-06-25

申请号：US17149216

申请日：2021-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Bongju Cho

IPC: H01L23/28 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/528 ,  H01L23/53238 ,  H01L24/14

Abstract: A semiconductor package includes: a first redistribution structure having a first surface and a second surface opposing the first surface, and including a first insulating layer and a first redistribution layer disposed on the first insulating layer; a semiconductor chip disposed on the first surface of the first redistribution structure, and including a connection pad electrically connected to the first redistribution layer and embedded in the first insulating layer; a vertical connection structure disposed on the first surface and electrically connected to the first redistribution layer; an encapsulant encapsulating at least a portion of each of the semiconductor chip and the vertical connection structure; a second redistribution structure disposed on the encapsulant and including a second redistribution layer electrically connected to the vertical connection structure; and a connection bump disposed on the second surface and electrically connected to the first redistribution layer.

公开(公告)号：US11804444B2

公开(公告)日：2023-10-31

申请号：US17008961

申请日：2020-09-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongjin Park ,  Myungsam Kang ,  Youngchan Ko ,  Seonho Lee

IPC: H01L23/538 ,  H01L23/373 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L23/3735 ,  H01L23/49827 ,  H01L23/49838 ,  H01L21/486 ,  H01L21/4857 ,  H01L2225/1094

Abstract: A semiconductor package includes; a semiconductor chip including a top surface and an opposing bottom surface, a heat dissipation structure including a lower adhesive layer adhered to the top surface of the semiconductor chip, a heat dissipation layer disposed on the lower adhesive layer, and a conductive layer disposed on the heat dissipation layer, a core layer including a cavity and a lower surface, wherein a combination of the semiconductor chip and the heat dissipation structure is disposed within the cavity, and a bottom re-wiring layer including a bottom re-wiring line connected to the semiconductor chip.

公开(公告)号：US11721620B2

公开(公告)日：2023-08-08

申请号：US17218356

申请日：2021-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam Kang ,  Youngchan Ko ,  Jeongseok Kim ,  Bongju Cho

IPC: H01L23/552 ,  H01L23/498 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/552 ,  H01L25/105 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A fan-out type semiconductor package includes: a frame including a cavity and a middle redistribution layer (RDL) structure at least partially surrounding the cavity; a semiconductor chip in the cavity; a lower RDL structure on the frame and electrically connected with the semiconductor chip and the middle RDL structure; an upper RDL structure on the frame and electrically connected with the middle RDL structure; an upper shielding pattern in the upper RDL structure to shield the semiconductor chip from electromagnetic interference (EMI); a lower shielding pattern in the lower RDL structure to shield the semiconductor chip from the EMI; and a side shielding pattern in the middle RDL structure to shield the semiconductor chip from the EMI. The upper shielding pattern and the lower shielding pattern have a thickness of no less than about 5 μm, and the side shielding pattern has a width of no less than about 5 μm.