公开(公告)号：US09466734B2

公开(公告)日：2016-10-11

申请号：US14325614

申请日：2014-07-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koichi Arai ,  Yasuaki Kagotoshi ,  Kenichi Hisada

IPC: H01L29/66 ,  H01L29/732 ,  H01L29/808 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L29/8083 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068

Abstract: To provide a semiconductor device having a vertical JFET excellent in off-state performance without reducing a production yield. A gate region quadrangular in the cross-section along a channel width direction is formed below a source region by impurity ion implantation. By first etching, the source region over the upper surface of the gate region is removed to separate therebetween. Then, the upper surface of the gate region is processed by second etching having an etching rate lower at the side surface than at the center of the gate region. The resulting gate region has a lower surface parallel to the substrate surface and an upper surface below a boundary between the source region and the channel formation region and having, in the cross-section along the channel width direction, a downward slope from the side surface to the center. As a result, a channel length with reduced variations can be obtained.

Abstract translation: 提供具有非常优异的截止状态的垂直JFET的半导体器件，而不降低产量。 通过杂质离子注入在源极区的下方形成沿通道宽度方向的截面中四边形的栅极区域。 通过首先蚀刻，去除栅极区域的上表面上方的源极区域以在其间分离。 然后，栅极区域的上表面通过第二蚀刻进行处理，其蚀刻速率在侧表面比在栅极区域的中心处更低。 所得到的栅极区域具有平行于基板表面的下表面和源区域和沟道形成区域之间的边界下方的上表面，并且在沿着沟道宽度方向的横截面中，从侧表面 到中心 结果，可以获得具有减小的变化的通道长度。

公开(公告)号：US09048264B2

公开(公告)日：2015-06-02

申请号：US14220447

申请日：2014-03-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuaki Kagotoshi ,  Koichi Arai ,  Natsuki Yokoyama ,  Haruka Shimizu

IPC: H01L21/337 ,  H01L21/00 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/808 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L29/0619 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/66068 ,  H01L29/66893 ,  H01L29/8083

Abstract: A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n+-type source layer on a surface of an n−-type drift layer formed on an n+-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n−-type drift layer with a silicon oxide film formed on the n−-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n−-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n−-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.

Abstract translation: 结型场效应晶体管的制造方法包括以下步骤：（a）在n +型SiC衬底上形成的n型漂移层的表面上形成n +型源极层; （b）通过用形成在用作掩模的n型漂移层上的氧化硅膜蚀刻n型漂移层的表面，形成以预定间隔设置的多个浅沟槽; （c）通过使用垂直离子注入方法通过用氮掺杂每个浅沟槽下方的n型漂移层来形成n型计数器掺杂层; （d）在氧化硅膜和浅沟槽的每个侧壁上形成侧壁间隔物; 和（e）通过使用垂直离子注入法，通过用铝掺杂每个浅沟槽下的n型漂移层来形成p型栅极层。

公开(公告)号：US09041049B2

公开(公告)日：2015-05-26

申请号：US13970586

申请日：2013-08-19

Applicant: Renesas Electronics Corporation

Inventor： Koichi Arai ,  Yasuaki Kagotoshi ,  Nobuo Machida ,  Natsuki Yokoyama ,  Haruka Shimizu

IPC: H01L29/66 ,  H01L29/36 ,  H01L29/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423 ,  H01L29/808

CPC classification number: H01L29/36 ,  H01L29/045 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/66909 ,  H01L29/8083

Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

Abstract translation: 通常，在诸如基于SiC的正常关断JFET的半导体有源元件中，其中杂质扩散速度显着低于硅中的杂质扩散速度，通过离子注入形成在源区中形成的沟槽的侧壁中形成栅极区。 然而，为了确保JFET的性能，需要高精度地控制栅极区域之间的面积。 此外，存在这样的问题，由于通过在源极区域中形成栅极区域而形成重掺杂的PN结，所以不能避免结电流的增加。 本发明提供一种常闭功率JFET及其制造方法，根据多次外延法形成栅极区域，该方法重复包括外延生长，离子注入和激活退火多次的工艺。

公开(公告)号：US20140339659A1

公开(公告)日：2014-11-20

申请号：US14452756

申请日：2014-08-06

Applicant: Renesas Electronics Corporation

Inventor： Koichi Arai

IPC: B81B3/00

CPC classification number: B81B3/0072 ,  B81B3/00 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00896 ,  B81C3/00 ,  B81C2201/056 ,  G01L9/0042 ,  G01L19/06 ,  H01L29/84 ,  H01L2224/13 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00

Abstract: In a method of manufacturing a semiconductor integrated circuit device having an MEMS element over a single semiconductor chip, the movable part of the MEMS element is fixed before the formation of a rewiring. After formation of the rewiring, the wafer is diced. Then, the movable part of the MEMS element is released by etching the wafer.

Abstract translation: 在制造在单个半导体芯片上具有MEMS元件的半导体集成电路器件的方法中，MEMS元件的可移动部件在形成重新布线之前被固定。 在重新布线形成之后，晶片被切割。 然后，通过蚀刻晶片来释放MEMS元件的可移动部分。