公开(公告)号：US09412750B2

公开(公告)日：2016-08-09

申请号：US15067444

申请日：2016-03-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/792

CPC classification number: H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

Abstract: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

Abstract translation: 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

公开(公告)号：US20160141396A1

公开(公告)日：2016-05-19

申请号：US15004972

申请日：2016-01-24

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi Arigane ,  Daisuke Okada ,  Digh Hisamoto

IPC: H01L29/66 ,  H01L29/423

CPC classification number: H01L29/66833 ,  H01L21/2815 ,  H01L21/28158 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/792

Abstract: To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy.

公开(公告)号：US09299715B2

公开(公告)日：2016-03-29

申请号：US14685093

申请日：2015-04-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

IPC: H01L21/28 ,  H01L27/115 ,  H01L29/792 ,  H01L29/423

CPC classification number: H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

Abstract: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

公开(公告)号：US20150145023A1

公开(公告)日：2015-05-28

申请号：US14548595

申请日：2014-11-20

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi Arigane ,  Daisuke Okada ,  Digh Hisamoto

IPC: H01L27/115 ,  H01L29/423 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/66833 ,  H01L21/2815 ,  H01L21/28158 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/792

Abstract: To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy.

Abstract translation: 提供具有改善特性的非易失性存储器的半导体器件。 在半导体器件中，非易失性存储器在控制栅电极部分和存储栅电极部分之间具有高k绝缘膜（高介电常数膜），并且外围电路区域的晶体管具有高k /金属构造。 布置在控制栅电极部分和存储栅电极部分之间的高k绝缘膜松弛在控制栅电极部分一侧的存储栅电极部分的端部（拐角部分）的电场强度。 这导致电荷累积部分（氮化硅膜）中电荷的不均匀分布的减少和擦除精度的提高。

公开(公告)号：US08963226B2

公开(公告)日：2015-02-24

申请号：US13970703

申请日：2013-08-20

Applicant: Renesas Electronics Corporation

Inventor： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC: H01L29/768 ,  H01L29/792 ,  G11C16/04 ,  H01L21/28 ,  H01L27/02 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

Abstract translation: 半导体存储器阵列包括具有第一电荷存储层和第一非易失性存储单元的第一非易失性存储单元，第一非易失性存储单元与第一存储单元相邻，具有第二电荷存储层和第二栅电极 。 第一电极和第二电极在垂直于第一方向的第二方向上延伸，第一电极具有在第一方向上朝向第二电极延伸的第一接触部分，并且第二电极具有朝向第一电极的第二接触部分 第一个方向 第一和第二接触位置分别沿第二方向移动，第一电极和第一接触部分与第二电极和第二接触部分电气分离。

公开(公告)号：US20140008716A1

公开(公告)日：2014-01-09

申请号：US13931874

申请日：2013-06-29

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yutaka Okuyama ,  Takashi Hashimoto ,  Daisuke Okada

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L21/823481 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66833

Abstract: When the width of an isolation region is reduced through the scaling of a memory cell to reduce the distance between the memory cell and an adjacent memory cell, the electrons or holes injected into the charge storage film of the memory cell are diffused into the portion of the charge storage film located over the isolation region to interfere with each other and possibly impair the reliability of the memory cell. In a semiconductor device, the charge storage film of the memory cell extends to the isolation region located between the adjacent memory cells. The effective length of the charge storage film in the isolation region is larger than the width of the isolation region. Here, the effective length indicates the length of the region of the charge storage film which is located over the isolation region and in which charges are not stored.

Abstract translation: 当通过存储单元的缩放来减小隔离区域的宽度以减小存储单元和相邻存储单元之间的距离时，注入到存储单元的电荷存储膜中的电子或空穴被扩散到 位于隔离区域上方的电荷存储膜彼此干涉并可能损害存储单元的可靠性。 在半导体器件中，存储单元的电荷存储膜延伸到位于相邻存储单元之间的隔离区域。 隔离区域中的电荷存储膜的有效长度大于隔离区域的宽度。 这里，有效长度表示位于隔离区上方的电荷存储膜的区域的长度，其中不存储电荷。