Invention Grant
- Patent Title: Fabrication method and structure of semiconductor non-volatile memory device
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Application No.: US14685093Application Date: 2015-04-13
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Publication No.: US09299715B2Publication Date: 2016-03-29
- Inventor: Digh Hisamoto , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Roberts Mlotkowski Safran & Cole, P.C.
- Agent Gregory E. Montone
- Priority: JPP2002-352040 20021204
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L27/115 ; H01L29/792 ; H01L29/423

Abstract:
A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.
Public/Granted literature
- US20150221664A1 FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE Public/Granted day:2015-08-06
Information query
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