公开(公告)号：US20150043265A1

公开(公告)日：2015-02-12

申请号：US13962702

申请日：2013-08-08

Applicant: QUALCOMM Incorporated

Inventor： Gregory Ameriada Uvieghara ,  Sei Seung Yoon

IPC: G11C17/18 ,  H03K3/356 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C16/12 ,  G11C17/16 ,  H03K3/356113

Abstract: A thin gate-oxide dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit is configured to bias the switched n-well to prevent voltage damage to the dual-mode PMOS transistor without the use of native transistors.

Abstract translation: 公开了一种薄栅氧化物双模PMOS晶体管，其具有第一工作模式，其中双模PMOS晶体管的开关n阱被偏置到高电压。 双模式PMOS晶体管具有第二工作模式，其中开关n阱被偏置成低于高电压的低电压。 双模式PMOS晶体管的尺寸和栅极氧化物厚度各自具有不能适应与高电压的永久连接的幅度。 n阱电压开关电路被配置为偏置开关n阱以防止对双模PMOS晶体管的电压损坏，而不使用天然晶体管。

公开(公告)号：US20140269112A1

公开(公告)日：2014-09-18

申请号：US13863989

申请日：2013-04-16

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Changho Jung ,  Sei Seung Yoon ,  Rakesh Vattikonda ,  Nishith Desai

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/1084 ,  G11C7/1096 ,  G11C11/419

Abstract: A write driver for a memory circuit includes a control circuit configured to: operate a first push-pull driver to generate a first drive signal in a first voltage domain at a first node based on an input signal in a second domain and in response to a mode select signal being in a first mode, wherein the first drive signal is at a same logic level as the input signal; operate a second push-pull driver to generate a second drive signal in the first voltage domain at a second node based on the input signal and in response to the mode select signal being in the first mode, wherein the second drive signal is at a complement logic level with respect to the input signal; and operate the first and second push-pull drivers to float the first and second nodes in response to the mode select signal being in a second mode.

Abstract translation: 用于存储器电路的写驱动器包括控制电路，该控制电路被配置为：基于第二域中的输入信号，并响应于第一推挽驱动器响应于第一推挽驱动器，在第一节点处的第一电压域中产生第一驱动信号 模式选择信号处于第一模式，其中第一驱动信号处于与输入信号相同的逻辑电平; 操作第二推挽驱动器以基于输入信号在第二节点处的第一电压域中产生第二驱动信号，并且响应于模式选择信号处于第一模式，其中第二驱动信号为补码 相对于输入信号的逻辑电平; 并且响应于所述模式选择信号处于第二模式，操作所述第一和第二推挽驱动器使所述第一和第二节点浮动。

公开(公告)号：US10049729B1

公开(公告)日：2018-08-14

申请号：US15708393

申请日：2017-09-19

Applicant: QUALCOMM Incorporated

Inventor： Esin Terzioglu ,  Sei Seung Yoon ,  Chulmin Jung ,  Bin Liang

IPC: G11C11/00 ,  G11C11/419

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may change a device operating voltage from a first voltage to a second voltage while the assist circuit is in a first state. The apparatus may also maintain the device operating voltage at the second voltage for a predetermined time. The apparatus may switch the assist circuit from the first state to a second state. The apparatus may adjust the device operating voltage to a third voltage after the predetermined time, wherein the second voltage is a voltage level between the first voltage and the third voltage. By transitioning the device operating voltage from the first voltage to the third voltage while at the same time preventing the assist circuit from entering particular read assist states, the apparatus may reduce a likelihood of read failures.

公开(公告)号：US09646681B1

公开(公告)日：2017-05-09

申请号：US15137952

申请日：2016-04-25

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Keejong Kim ,  Sei Seung Yoon

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/4125 ,  H01L28/00

Abstract: A memory and a method for operating a memory are provided. The memory includes a memory cell having a first circuit to store a bit and a second circuit to decouple the stored bit from a power supply and from a return. The method includes storing a bit in a memory cell by a first circuit and decoupling the stored bit from a power supply and a return by a second circuit. Another memory is provided. The memory includes a memory cell having means for storing a bit by a feedback and means for disabling the feedback.

公开(公告)号：US20160299517A1

公开(公告)日：2016-10-13

申请号：US14684128

申请日：2015-04-10

Applicant: QUALCOMM Incorporated

Inventor： Sanjay Bhagawan Patil ,  Daniel Stasiak ,  Martin Pierre Saint-Laurent ,  Rui Li ,  Bin Liang ,  Sei Seung Yoon ,  Chulmin Jung

IPC: G05F1/10

CPC classification number: G05F1/10 ,  G06F1/26 ,  G06F1/263 ,  G06F1/3287 ,  G06F1/329 ,  H02M1/32

Abstract: Voltage droop control is disclosed. A device includes a first component coupled to an external power supply and a second component coupled to the external power supply. The first component includes a first input configured to receive a first voltage, a first internal power supply configured to be charged by the external power supply in response to the first voltage corresponding to a first logical value, and a voltage droop controller configured to output a second voltage via a first output. The second voltage corresponds to the first logical value in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second component includes a second input configured to receive the second voltage from the first output.

Abstract translation: 公开了电压下降控制。 一种设备包括耦合到外部电源的第一组件和耦合到外部电源的第二组件。 第一组件包括被配置为接收第一电压的第一输入，被配置为响应于对应于第一逻辑值的第一电压由外部电源充电的第一内部电源;以及电压下降控制器，被配置为输出 经由第一输出的第二电压。 响应于满足第二电压电平的第一内部电源的第一电压电平，第二电压对应于第一逻辑值。 第二组件包括被配置为从第一输出接收第二电压的第二输入。

公开(公告)号：US09373388B1

公开(公告)日：2016-06-21

申请号：US14699957

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Fahad Ahmed ,  Chulmin Jung ,  Sei Seung Yoon

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/12 ,  G11C7/06

CPC classification number: G11C11/419 ,  G11C7/062 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12

Abstract: A sense amplifier is provided with a pair of first pull-up transistors that are configured to charge a corresponding pair of output terminals while a delayed sense enable signal is not asserted and to stop charging the corresponding pair of output terminals while the delayed sense enable signal is asserted.

Abstract translation: 读出放大器设置有一对第一上拉晶体管，其被配置为对相应的一对输出端子充电，同时延迟感测使能信号未被置位并且在延迟的感测使能信号的同时停止对相应的输出端子对的充电 被断言。

公开(公告)号：US09202555B2

公开(公告)日：2015-12-01

申请号：US13656593

申请日：2012-10-19

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Nishith Desai ,  Sei Seung Yoon

IPC: G11C11/00 ,  G11C11/418 ,  G11C8/08 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C8/08 ,  G11C11/419

Abstract: A write-assisted memory. The write-assisted memory includes a word-line decoder that is implemented within a low VDD power domain. The write-assisted memory also includes a write-segment controller that is partially implemented within the low VDD power domain and is partially implemented within a high VDD power domain. The write-assisted memory further includes a local write word-line decoder that is implemented within the high VDD power domain.

Abstract translation: 写辅助记忆。 写辅助存储器包括在低VDD功率域内实现的字线解码器。 写辅助存储器还包括写入段控制器，其部分地在低VDD功率域内实现，并且部分地在高VDD功率域内实现。 写辅助存储器还包括在高VDD功率域内实现的本地写字线解码器。

公开(公告)号：US09165619B2

公开(公告)日：2015-10-20

申请号：US13919255

申请日：2013-06-17

Applicant: QUALCOMM Incorporated

Inventor： Hui Song ,  Sei Seung Yoon ,  Jongwon Lee

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/18

CPC classification number: G11C7/12 ,  G11C7/1012 ,  G11C7/18 ,  G11C2207/005

Abstract: The disclosure relates to an apparatus for reading data from a memory circuit that includes at least two memory banks. The apparatus includes a first multiplexer configured to generate data at a first output from a first selected one of a first set of bit lines of a first memory bank based on a select signal. The apparatus also includes a second multiplexer configured to generate data at a second output from a second selected one of a second set of bit lines of a second memory bank based on the select signal. Additionally, the apparatus includes a gating device configured to gate the data from either the first and second multiplexer outputs based on an enable signal. And, the apparatus includes an interface circuit configured to produce the gated data on a global bit line.

Abstract translation: 本公开涉及一种用于从包括至少两个存储体的存储器电路读取数据的装置。 该装置包括第一多路复用器，其被配置为基于选择信号从第一存储体组的第一组位线中的第一选定一个产生第一输出的数据。 该装置还包括第二多路复用器，其被配置为基于选择信号从第二存储器组的第二组位线中的第二选定的一个产生第二输出端的数据。 另外，该装置包括门控装置，其配置为基于使能信号来从第一和第二多路复用器输出端口选择数据。 并且，该装置包括被配置为在全局位线上产生门控数据的接口电路。

公开(公告)号：US20150294697A1

公开(公告)日：2015-10-15

申请号：US14251315

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Rui Li ,  David Li ,  Tahseen Shakir ,  Sei Seung Yoon

IPC: G11C7/06 ,  G11C11/419

CPC classification number: G11C7/065 ,  G11C11/419

Abstract: A sense amplifier is provided that includes a skewed latch that latches a voltage difference developed responsive to a read operation on an accessed memory cell. The skewed latch includes a loaded logic gate that is cross-coupled with an unloaded logic gate. The loaded logic gate drives the unloaded logic gate and an output transistor whereas the unloaded logic gate drives only the loaded logic gate.

Abstract translation: 提供了一种读出放大器，其包括倾斜的锁存器，其锁存响应于对所访问的存储器单元的读取操作产生的电压差。 偏斜锁存器包括与卸载逻辑门交叉耦合的加载逻辑门。 加载的逻辑门驱动无载逻辑门和输出晶体管，而无负载逻辑门仅驱动加载的逻辑门。

公开(公告)号：US09082481B2

公开(公告)日：2015-07-14

申请号：US14503861

申请日：2014-10-01

Applicant: QUALCOMM Incorporated

Inventor： Esin Terzioglu ,  Nishith Desai ,  Rakesh Vattikonda ,  ChangHo Jung ,  Sei Seung Yoon

IPC: G11C15/04 ,  G11C15/00

CPC classification number: G11C15/04 ,  G11C15/00 ,  G11C15/043 ,  G11C15/046

Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.