公开(公告)号：US08943293B2

公开(公告)日：2015-01-27

申请号：US14219034

申请日：2014-03-19

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward Koob ,  Ajay Anant Ingle ,  Lucian Codrescu ,  Jian Shen

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34 ,  G06F12/08 ,  G06F17/50

CPC classification number: G06F12/0895 ,  G06F12/0802 ,  G06F12/0864 ,  G06F17/505 ,  G06F2212/2515 ,  G06F2212/601

Abstract: A method includes receiving an address at a tag state array of a cache, wherein the cache is configurable to have a first size and a second size that is smaller than the first size. The method further includes identifying a first portion of the address as a set index, wherein the first portion has a same number of bits when the cache has the first size as when the cache has the second size. The method further includes using the set index to locate at least one tag field of the tag state array, identifying a second portion of the address to compare to a value stored at the at least one tag field, locating at least one state field of the tag state array that is associated with a particular tag field that matches the second portion, identifying a cache line based on a comparison of a third portion of the address to at least one status bit of the at least one state field when the cache has the second size, and retrieving the cache line.

Abstract translation: 一种方法包括在高速缓存的标签状态阵列处接收地址，其中高速缓存可配置为具有小于第一大小的第一大小和第二大小。 所述方法还包括将所述地址的第一部分识别为设置索引，其中当所述高速缓冲存储器具有所述第一大小时，所述第一部分具有相同的位数，就像所述高速缓存具有所述第二大小一样。 所述方法还包括使用所述设置索引来定位所述标签状态阵列的至少一个标签字段，识别所述地址的第二部分以与存储在所述至少一个标签字段处的值进行比较，以定位所述标签状态阵列的至少一个状态字段 标签状态阵列，其与与第二部分匹配的特定标签字段相关联，基于当高速缓存具有该地址时，该地址的第三部分与至少一个状态字段的至少一个状态位的比较来识别高速缓存行 第二大小，并检索高速缓存行。

公开(公告)号：US20140201494A1

公开(公告)日：2014-07-17

申请号：US13741981

申请日：2013-01-15

Applicant: QUALCOMM INCORPORATED

Inventor： Suresh K. Venkumahanti ,  Erich J. Plondke ,  Lucian Codrescu ,  Shane M. Mahon ,  Rahul R. Toley ,  Fadi A. Hamdan

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/1036 ,  G06F2212/652

Abstract: An apparatus includes a translation lookaside buffer (TLB). The TLB includes at least one entry that includes an entry virtual address and an entry page size indication corresponding to an entry page. The apparatus also includes input logic configured to receive an input page size indication and an input virtual address corresponding to an input page. The apparatus further includes overlap checking logic configured to determine, based at least in part on the entry page size indication and the input page size indication, whether the input page overlaps the entry page.

Abstract translation: 一种装置包括翻译后备缓冲器（TLB）。 TLB包括至少一个条目，其包括条目虚拟地址和对应于条目页面的条目页面大小指示。 该装置还包括被配置为接收输入页面大小指示和与输入页面相对应的输入虚拟地址的输入逻辑。 该装置还包括重叠检查逻辑，其被配置为至少部分地基于条目页面大小指示和输入页面大小指示来确定输入页面是否与入口页面重叠。

公开(公告)号：US20140201449A1

公开(公告)日：2014-07-17

申请号：US13741917

申请日：2013-01-15

Applicant: QUALCOMM Incorporated

Inventor： Peter G. Sassone ,  Suresh K. Venkumahanti ,  Lucian Codrescu

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F9/3455 ,  G06F9/3832 ,  G06F2212/6082

Abstract: In a particular embodiment, a method, includes identifying one or more way prediction characteristics of an instruction. The method also includes selectively reading, based on identification of the one or more way prediction characteristics, a table to identify an entry of the table associated with the instruction that identifies a way of a data cache. The method further includes making a prediction whether a next access of the data cache based, on the instruction will access the way.

Abstract translation: 在特定实施例中，一种方法包括识别指令的一种或多种方式预测特性。 该方法还包括基于一个或多个方式预测特征的识别来选择性地读取用于标识与标识数据高速缓存的方式相关联的表的条目的表。 该方法还包括基于指令访问数据高速缓存的下一次访问来进行预测。

公开(公告)号：US10474461B2

公开(公告)日：2019-11-12

申请号：US15272613

申请日：2016-09-22

Applicant: QUALCOMM Incorporated

Inventor： Eric Mahurin ,  Lucian Codrescu

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F15/80

Abstract: A method of determining an execution order of memory operations performed by a processor includes executing at least one single-instruction, multiple-data (SIMD) scatter operation by the processor to store data to a memory. The method further includes executing one or more instructions by the processor to determine the execution order of a set of memory operations. The set of memory operations includes the at least one SIMD scatter operation.

公开(公告)号：US10437591B2

公开(公告)日：2019-10-08

申请号：US13777314

申请日：2013-02-26

Applicant: Qualcomm Incorporated

Inventor： Michael R. McDonald ,  Erich J. Plondke ,  Pavel Potoplyak ,  Lucian Codrescu ,  Richard Kuo ,  Bryan C. Bayerdorffer

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/50 ,  G06F9/455 ,  G06F9/48

Abstract: An apparatus includes a first processor having a first instruction set and a second processor having a second instruction set that is different than the first instruction set. The apparatus also includes a memory storing at least a portion of an operating system. The operating system is concurrently executable on the first processor and the second processor.

公开(公告)号：US09715392B2

公开(公告)日：2017-07-25

申请号：US14473947

申请日：2014-08-29

Applicant: QUALCOMM Incorporated

Inventor： Suresh Kumar Venkumahanti ,  Ankit Ghiya ,  Peter Gene Sassone ,  Lucian Codrescu ,  Suman Mamidi

IPC: G06F9/38

CPC classification number: G06F9/3885 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3891

Abstract: A method includes identifying, at a scheduling unit, a resource conflict at a shared processing resource that is accessible by a first processing cluster and by a second processing cluster, where the first processing cluster, the second processing cluster, and the shared processing resource are included in a very long instruction word (VLIW) processing unit. The method also includes resolving the resource conflict.

公开(公告)号：US09632781B2

公开(公告)日：2017-04-25

申请号：US13777297

申请日：2013-02-26

Applicant: Qualcomm Incorporated

Inventor： Ajay A. Ingle ,  Marc M. Hoffman ,  Jose Fridman ,  Lucian Codrescu

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/345

CPC classification number: G06F9/30105 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30163 ,  G06F9/345 ,  G06F9/3885

Abstract: Techniques are provided for executing a vector alignment instruction. A scalar register file in a first processor is configured to share one or more register values with a second processor, the one or more register values accessed from the scalar register file according to an Rt address specified in a vector alignment instruction, wherein a start location is determined from one of the shared register values. An alignment circuit in the second processor is configured to align data identified between the start location within a beginning Vu register of a vector register file (VRF) and an end location of a last Vu register of the VRF according to the vector alignment instruction. A store circuit is configured to select the aligned data from the alignment circuit and store the aligned data in the vector register file according to an alignment store address specified by the vector alignment instruction.

公开(公告)号：US20160077835A1

公开(公告)日：2016-03-17

申请号：US14950612

申请日：2015-11-24

Applicant: QUALCOMM Incorporated

Inventor： Sergei Larin ,  Lucian Codrescu ,  Anshuman Das Gupta

IPC: G06F9/30

Abstract: A system for translating compressed instructions to instructions in an executable format is described. A translation unit is configured to decompress compressed instructions into a native instruction format using X and Y indices accessed from a memory, a translation memory, and a program specified mix mask. A level 1 cache is configured to store the native instruction format for each compressed instruction. The memory may be configured as a paged instruction cache to store pages of compressed instructions intermixed with pages of uncompressed instructions. Methods of determining a mix mask for efficiently translating compressed instructions is also described. A genetic method uses pairs of mix masks as genes from a seed population of mix masks that are bred and may be mutated to produce pairs of offspring mix masks to update the seed population. A mix mask for efficiently translating compressed instructions is determined from the updated seed population.

Abstract translation: 描述用于将压缩指令翻译成可执行格式的指令的系统。 翻译单元被配置为使用从存储器，翻译存储器和程序指定的混合掩码访问的X和Y索引将压缩指令解压缩为本地指令格式。 一级缓存被配置为存储每个压缩指令的本机指令格式。 存储器可以被配置为分页指令高速缓存以存储与未压缩指令的页面混合的压缩指令的页面。 还描述了确定用于有效翻译压缩指令的混合掩模的方法。 遗传方法使用成对的混合掩模作为来自种植混合掩模的种子群体的基因，并且可以被突变以产生成对的后代混合掩模以更新种子群体。 从更新的种子群体确定用于有效地翻译压缩指令的混合掩模。

公开(公告)号：US20160062770A1

公开(公告)日：2016-03-03

申请号：US14473947

申请日：2014-08-29

Applicant: QUALCOMM Incorporated

Inventor： Suresh Kumar Venkumahanti ,  Ankit Ghiya ,  Peter Gene Sassone ,  Lucian Codrescu ,  Suman Mamidi

IPC: G06F9/38

CPC classification number: G06F9/3885 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3891

Abstract: A method includes identifying, at a scheduling unit, a resource conflict at a shared processing resource that is accessible by a first processing cluster and by a second processing cluster, where the first processing cluster, the second processing cluster, and the shared processing resource are included in a very long instruction word (VLIW) processing unit. The method also includes resolving the resource conflict.

Abstract translation: 一种方法包括在调度单元处识别由第一处理集群和第二处理集群可访问的共享处理资源处的资源冲突，其中第一处理集群，第二处理集群和共享处理资源是 包括在一个很长的指令字（VLIW）处理单元中。 该方法还包括解决资源冲突。

公开(公告)号：US09141544B2

公开(公告)日：2015-09-22

申请号：US13655593

申请日：2012-10-19

Applicant: QUALCOMM Incorporated

Inventor： Manojkumar Pyla ,  Lucian Codrescu

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F12/0888 ,  G06F2212/601

Abstract: In a particular embodiment, a method of managing a cache memory includes, responsive to a cache size change command, changing a mode of operation of the cache memory to a write through/no allocate mode. The method also includes processing instructions associated with the cache memory while executing a cache clean operation when the mode of operation of the cache memory is the write through/no allocate mode. The method further includes after completion of the cache clean operation, changing a size of the cache memory and changing the mode of operation of the cache to a mode other than the write through/no allocate mode.

Abstract translation: 在特定实施例中，管理高速缓冲存储器的方法响应于高速缓存大小改变命令，将高速缓冲存储器的操作模式改变为写/无分配模式。 当高速缓冲存储器的操作模式是写/无分配模式时，该方法还包括处理与高速缓存存储器相关联的指令，同时执行高速缓存清理操作。 该方法还包括在完成高速缓存清理操作之后，改变高速缓冲存储器的大小并将高速缓存的操作模式改变为除了写/无分配模式以外的模式。