公开(公告)号：US20140281328A1

公开(公告)日：2014-09-18

申请号：US13842515

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Shree Krishna Pandey ,  Dexter T. Chun

IPC: G11C7/22

CPC classification number: G11C7/227 ,  G06F1/10 ,  G06F13/1689 ,  G06F13/4243

Abstract: A memory interface includes circuitry configured for applying a variable delay to a portion of a data signal and applying a variable delay to a data strobe. The delayed data strobe samples the delayed portion of the data signal. Delayed portions of the data signal are spaced away from non-delayed portions of the data signal by alternating the routing of delayed bits and non-delayed bits of the data signal. A training block determines and sets a value of the variable delay corresponding to a largest value of a number of recorded eye aperture widths.

Abstract translation: 存储器接口包括经配置以将可变延迟应用于数据信号的一部分并将可变延迟应用于数据选通的电路。 延迟数据选通对数据信号的延迟部分进行采样。 通过交替数据信号的延迟位和非延迟位的路由，数据信号的延迟部分与数据信号的非延迟部分间隔开。 训练块确定并设置与记录的眼孔宽度的数量的最大值相对应的可变延迟的值。

公开(公告)号：US20140253173A1

公开(公告)日：2014-09-11

申请号：US13787926

申请日：2013-03-07

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter T. Chun ,  Sumeet S. Sethi ,  John D. Eaton ,  Vinodh R. Cuppu ,  Vikram Arora ,  Vaishnav Srinivas ,  Muhammad A. Muneer ,  Isaac D. Berk

IPC: H03K19/0175

CPC classification number: H04L25/0278 ,  G06F13/4086 ,  H03K19/0005 ,  H03K19/017545 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.

Abstract translation: 一种控制信号终止的方法包括：提供用于选择性地终止在双向数据总线上在第一设备处接收的信号的第一逻辑，提供用于选择性地终止在双向数据总线上的第二设备处接收的信号的第二逻辑，从第一设备发送第一信号 以第一速度传送到双向数据总线上的第二设备，在停止发送第一信号之后停止发送第一信号，使得第二逻辑能够使第二设备的参考电压从第一电平移位到 在第二设备启用第二逻辑之后，以更高的速度在双向数据总线上从第一设备向第二设备发送第二信号，并且基于在第一设备处接收到的信号的速度来控制第一逻辑 在双向数据总线上。

公开(公告)号：US20140164690A1

公开(公告)日：2014-06-12

申请号：US13781366

申请日：2013-02-28

Applicant: QUALCOMM INCORPORATED

Inventor： Subrato K. De ,  Richard A. Stewart ,  Gheorghe Calin Cascaval ,  Dexter T. Chun

IPC: G06F12/06

CPC classification number: G06F12/023 ,  G06F12/0607 ,  G06F12/0638 ,  G06F2212/1044 ,  G11C7/1072 ,  Y02D10/13

Abstract: Systems and methods are provided for allocating memory to dissimilar memory devices. An exemplary embodiment includes a method for allocating memory to dissimilar memory devices. An interleave bandwidth ratio is determined, which comprises a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio to define two or more memory zones having different performance levels. Memory address requests are allocated to the memory zones based on a quality of service (QoS).

Abstract translation: 提供了系统和方法，用于将存储器分配给不同的存储器件。 示例性实施例包括用于将不同的存储器件分配存储器的方法。 确定交织带宽比，其包括两个或多个不同存储器件的带宽比。 不同的存储器件根据交织带宽比进行交织以定义具有不同性能级别的两个或多个存储器区域。 基于服务质量（QoS）将内存地址请求分配给内存区域。

公开(公告)号：US20130326188A1

公开(公告)日：2013-12-05

申请号：US13752427

申请日：2013-01-29

Applicant: QUALCOMM INCORPORATED

Inventor： Jungwon Suh ,  Dexter T. Chun

IPC: G06F12/10

CPC classification number: G11C5/06 ,  G11C5/04 ,  G11C5/063 ,  G11C7/02 ,  G11C7/222 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: In an embodiment, a stacked package-on-package system has a memory die and a logic die. The memory die comprises a first memory and a second memory, each operated independently of the other, and each having an inter-chip interface electrically connected to the logic die. The logic die has two independent clock sources, one to provide a first clock signal to the first memory, and the other clock source to provide a second clock signal to the second memory.

Abstract translation: 在一个实施例中，堆叠封装的封装系统具有存储器管芯和逻辑管芯。 存储器管芯包括第一存储器和第二存储器，每个存储器和第二存储器分别独立于另一个存储器和第二存储器，并且每个具有电连接到逻辑管芯的芯片间接口。 逻辑管芯具有两个独立的时钟源，一个用于向第一存储器提供第一时钟信号，另一个时钟源提供第二时钟信号给第二存储器。