EDGE REFLECTION REDUCTION
    27.
    发明申请

    公开(公告)号:US20170317124A1

    公开(公告)日:2017-11-02

    申请号:US15430071

    申请日:2017-02-10

    Abstract: An image sensor package includes an image sensor with a pixel array disposed in a semiconductor material. A first transparent shield is adhered to the semiconductor material, and the pixel array is disposed between the semiconductor material and the first transparent shield. The image sensor package further includes a second transparent shield, where the first transparent shield is disposed between the pixel array and the second transparent shield. A light blocking layer is disposed between the first transparent shield and the second transparent shield, and the light blocking layer is disposed to prevent light from reflecting off edges of the first transparent shield into the pixel array.

    High near infrared sensitivity image sensor

    公开(公告)号:US09799699B2

    公开(公告)日:2017-10-24

    申请号:US14494960

    申请日:2014-09-24

    Abstract: An image sensor includes a plurality of photodiodes disposed proximate to a frontside of a first semiconductor layer to accumulate image charge in response to light directed into the frontside of the first semiconductor layer. A plurality of pinning wells is disposed in the first semiconductor layer. The pinning wells separate individual photodiodes included in the plurality of photodiodes. A plurality of dielectric layers is disposed proximate to a backside of the first semiconductor layer. The dielectric layers are tuned such that light having a wavelength substantially equal to a first wavelength included in the light directed into the frontside of the first semiconductor layer is reflected from the dielectric layers back to a respective one of the plurality of photodiodes disposed proximate to the frontside of the first semiconductor layer.

    Method of fabricating multi-wafer image sensor

    公开(公告)号:US09748308B2

    公开(公告)日:2017-08-29

    申请号:US15166002

    申请日:2016-05-26

    Abstract: A method of fabricating an image system includes forming a first wafer that includes a first semiconductor substrate and a first interconnect layer. A pixel array is formed in an imaging region of the first semiconductor substrate and a first insulation-filled trench is formed in a peripheral circuit region of the first semiconductor substrate. Additionally, a second wafer is formed that includes a second semiconductor substrate and a second interconnect layer. A second insulation-filled trench is formed in a second semiconductor substrate, and the first wafer is bonded to the second wafer. A third interconnect layer of a third wafer is bonded to the second wafer. At least one deep via cavity is formed through the first and second interconnect layers and through the first and second insulation-filled trenches. The at least one deep via cavity is filled with a conductive material to form a deep via.

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