公开(公告)号：US20220358971A1

公开(公告)日：2022-11-10

申请号：US17669189

申请日：2022-02-10

Applicant: Micron Technology, Inc.

Inventor： Che-Chi Lee ,  Terrence B. McDaniel ,  Kehao Zhang ,  Albert P. Chan ,  Clement Jacob ,  Luca Fumagalli ,  Vinay Nair

IPC: G11C5/10 ,  H01L27/108 ,  H01L49/02 ,  G11C11/405 ,  H01L27/06

Abstract: Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220285357A1

公开(公告)日：2022-09-08

申请号：US17194859

申请日：2021-03-08

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Vinay Nair ,  Devesh Dadhich Shreeram ,  Ashwin Panday ,  Kangle Li ,  Zhiqiang Xie ,  Silvia Borsari ,  Mohd Kamran Akhtar ,  Si-Woo Lee

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

公开(公告)号：US11309315B2

公开(公告)日：2022-04-19

申请号：US16943108

申请日：2020-07-30

Applicant: Micron Technology, Inc.

Inventor： Terrence B. McDaniel ,  Si-Woo Lee ,  Vinay Nair ,  Luca Fumagalli

IPC: H01L27/108 ,  G11C5/06

Abstract: Systems, methods, and apparatuses are provided for digit line formation for horizontally oriented access devices. One example method includes forming layers of a first dielectric material, a low doped semiconductor material, and a second dielectric material, in repeating iterations vertically to form a vertical stack, forming a vertical opening in the vertical stack, selectively etching the second dielectric material to form a horizontal opening in the second dielectric material, gas phase doping a dopant on a top surface of the low doped semiconductor material in the horizontal opening to form a source/drain region, forming a high doped semiconductor material in the horizontal opening, selectively etching the high doped semiconductor material formed in the horizontal opening such that a portion of the high doped semiconductor material remains, and converting the remaining high doped semiconductor material to a conductive material having a different characteristic from the remaining high doped semiconductor material.

公开(公告)号：US20220037334A1

公开(公告)日：2022-02-03

申请号：US16943108

申请日：2020-07-30

Applicant: Micron Technology, Inc.

Inventor： Terrence B. McDaniel ,  Si-Woo Lee ,  Vinay Nair ,  Luca Fumagalli

IPC: H01L27/108 ,  G11C5/06

Abstract: Systems, methods, and apparatuses are provided for digit line formation for horizontally oriented access devices. One example method includes forming layers of a first dielectric material, a low doped semiconductor material, and a second dielectric material, in repeating iterations vertically to form a vertical stack, forming a vertical opening in the vertical stack, selectively etching the second dielectric material to form a horizontal opening in the second dielectric material, gas phase doping a dopant on a top surface of the low doped semiconductor material in the horizontal opening to form a source/drain region, forming a high doped semiconductor material in the horizontal opening, selectively etching the high doped semiconductor material formed in the horizontal opening such that a portion of the high doped semiconductor material remains, and converting the remaining high doped semiconductor material to a conductive material having a different characteristic from the remaining high doped semiconductor material.

公开(公告)号：US20190267379A1

公开(公告)日：2019-08-29

申请号：US16412750

申请日：2019-05-15

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Kris K. Brown ,  Raghunath Singanamalla ,  Vinay Nair ,  Fawad Ahmed ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L29/94 ,  H01L27/06 ,  H01L49/02 ,  H01L27/02 ,  H01L29/10 ,  H01L29/78

Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

公开(公告)号：US10056386B2

公开(公告)日：2018-08-21

申请号：US15664217

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Kris K. Brown ,  Raghunath Singanamalla ,  Vinay Nair ,  Fawad Ahmed ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L27/06 ,  H01L29/78 ,  H01L29/10 ,  H01L49/02 ,  H01L27/02 ,  H01L29/08 ,  H01L23/528

CPC classification number: H01L27/108 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/10841 ,  H01L27/10864 ,  H01L28/60 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/7827 ,  H01L29/945

Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

公开(公告)号：US20180061835A1

公开(公告)日：2018-03-01

申请号：US15664161

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Gloria Yang ,  Suraj J. Mathew ,  Raghunath Singanamalla ,  Vinay Nair ,  Scott J. Derner ,  Michael Amiel Shore ,  Brent Keeth ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L27/06 ,  H01L29/423 ,  H01L49/02 ,  H01L29/78

CPC classification number: H01L27/108 ,  G11C11/403 ,  H01L23/528 ,  H01L27/0688 ,  H01L28/90 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42376 ,  H01L29/7827

Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.

公开(公告)号：US20240064972A1

公开(公告)日：2024-02-22

申请号：US17892603

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Terrence B. Mcdaniel ,  Guangjun Yang ,  Vinay Nair

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10894

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes data lines; first structures located in a first region, electrically separated from each other, and including first conductive contacts coupled to the data lines; second conductive contacts located in the first region and coupled to memory elements of the apparatus; second structures located in a second region, electrically separated from each other, and including respective gates of transistors in the second region; a first dielectric material formed in the second region and including a first portion and a second portion, the first portion formed at a first side of a structure among the second structures, the second portion formed at a second side first of the structure; and a second dielectric material formed over the first structures and the second structure. A portion of the second dielectric material contacts the first portion of the first dielectric material.

公开(公告)号：US20240038588A1

公开(公告)日：2024-02-01

申请号：US17815359

申请日：2022-07-27

Applicant: Micron Technology, Inc.

Inventor： Terrence B. McDaniel ,  Vinay Nair ,  Russell A. Benson ,  Christopher W. Petz ,  Si-Woo Lee ,  Silvia Borsari ,  Ping Chieh Chiang ,  Luca Fumagalli

IPC: H01L21/768 ,  H01L27/108

CPC classification number: H01L21/76897 ,  H01L27/10855 ,  H01L27/10885

Abstract: A method of forming a microelectronic device comprises forming interlayer dielectric material over a base structure comprising semiconductive structures separated from one another by insulative structures. Sacrificial line structures separated from one another by trenches are formed over the interlayer dielectric material. The sacrificial line structures horizontally overlap some of the semiconductive structures, and the trenches horizontally overlap some other of the semiconductive structures. Plug structures are formed within horizontal areas of the trenches and extend through the interlayer dielectric material and into the some other of the semiconductive structures. The sacrificial line structures are replaced with additional trenches. Conductive contact structures are formed within horizontal areas of the additional trenches and extend through the interlayer dielectric material and into the some of the semiconductive structures. Conductive line structures are formed within the additional trenches and in contact with the conductive contact structures.

公开(公告)号：US20230345708A1

公开(公告)日：2023-10-26

申请号：US17729450

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang ,  Terrence B. McDaniel ,  Russell A. Benson ,  Vinay Nair

IPC: H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/10888 ,  H01L27/10897

Abstract: Methods, apparatuses, and systems related to a sense line and cell contact for a semiconductor structure are described. An example apparatus includes a first source/drain region and a second source/drain region, where the first source/drain region and the second source/drain region are separated by a channel, a gate opposing the channel, a sense line material coupled to the first source/drain region by a cell contact, where the cell contact is made from a combination of a first polysilicon material and a second polysilicon material, and a storage node coupled to the second source/drain region.