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公开(公告)号：US20230343815A1
公开(公告)日：2023-10-26
申请号：US17726965
申请日：2022-04-22
发明人： Ryan L. Meyer , Vinay Nair , Andrea Gotti , Kevin Shea , Kyle R. Knori
IPC分类号： H01L49/02 , H01L27/108
CPC分类号： H01L28/60 , H01L27/1085
摘要： Methods, apparatuses, and systems related to depositing a storage node material are described. An example method includes forming a semiconductor structure including a support structure having a first silicate material over a bottom nitride material, a first nitride material over the first silicate material, a second silicate material over the first nitride material, and a second nitride material over the second silicate material. The method further includes removing portions of the second nitride material. The method further includes depositing a third silicate material over the second nitride material and a portion of the second silicate material. The method further includes forming an opening through the semiconductor structure. The method further includes depositing a storage node material within the opening.
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公开(公告)号：US20220059469A1
公开(公告)日：2022-02-24
申请号：US16999817
申请日：2020-08-21
发明人： Russell A. Benson , Davide Colombo , Yan Li , Terrence B. McDaniel , Vinay Nair , Silvia Borsari
IPC分类号： H01L23/552 , H01L27/108
摘要： A method of forming a microelectronic device comprises forming a conductive shielding material over a conductive shielding structure and a first dielectric structure horizontally adjacent the conductive shielding structure. A second dielectric structure is formed on first dielectric structure and horizontally adjacent the conductive shielding material. The conductive shielding material and the second dielectric structure are patterned to form fin structures extending in parallel in a first horizontal direction. Each of the fin structures comprises two dielectric end structures integral with remaining portions of the second dielectric structure, and an additional conductive shielding structure interposed between the two dielectric end structures in the first horizontal direction. Conductive lines are formed to extend in parallel in the first horizontal direction and to horizontally alternate with the fin structures in a second horizontal direction orthogonal to the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.
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公开(公告)号：US10157926B2
公开(公告)日：2018-12-18
申请号：US15664161
申请日：2017-07-31
发明人： Gloria Yang , Suraj J. Mathew , Raghunath Singanamalla , Vinay Nair , Scott J. Derner , Michael Amiel Shore , Brent Keeth , Fatma Arzum Simsek-Ege , Diem Thy N. Tran
IPC分类号： H01L27/108 , H01L49/02 , H01L29/423 , H01L29/78 , G11C11/403 , H01L23/528 , H01L27/06 , H01L29/08 , H01L29/10
摘要： Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.
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公开(公告)号：US20240292603A1
公开(公告)日：2024-08-29
申请号：US18505462
申请日：2023-11-09
IPC分类号： H10B12/00 , H01L21/762
CPC分类号： H10B12/482 , H01L21/76224 , H10B12/02 , H10B12/485
摘要： Systems, methods and apparatus are provided for damascene digit lines. For instance, a damascene digit line can be formed by forming a plurality of dummy digit lines on a semiconductor substrate that are separated by a first set of vertical trenches, depositing a sacrificial insulating material in the first set of vertical trenches, forming, and depositing an insulating fill material in, a second set of vertical trenches, forming, and depositing a nitride material in, nitride material deposition spaces; removing at least a portion of the semiconductor substrate to form plurality of cell contact deposition spaces, forming cell contacts in the cell contact deposition spaces, removing the dummy digit lines to form a plurality of vertical openings, removing nitride material to form expanded vertical opening, depositing a digit line insulating material in the expanded vertical openings to form digit line deposition spaces, and forming digit lines.
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公开(公告)号：US11282548B1
公开(公告)日：2022-03-22
申请号：US17307686
申请日：2021-05-04
发明人： Che-Chi Lee , Terrence B. McDaniel , Kehao Zhang , Albert P. Chan , Clement Jacob , Luca Fumagalli , Vinay Nair
IPC分类号： G11C5/10 , H01L27/108 , H01L49/02 , G11C11/405 , H01L27/06
摘要： Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.
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公开(公告)号：US11094697B2
公开(公告)日：2021-08-17
申请号：US16183468
申请日：2018-11-07
发明人： Gloria Yang , Suraj J. Mathew , Raghunath Singanamalla , Vinay Nair , Scott J. Derner , Michael Amiel Shore , Brent Keeth , Fatma Arzum Simsek-Ege , Diem Thy N. Tran
IPC分类号： H01L27/108 , G11C11/403 , H01L49/02 , H01L29/423 , H01L29/78 , H01L23/528 , H01L27/06 , H01L29/08 , H01L29/10
摘要： Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.
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公开(公告)号：US10854611B2
公开(公告)日：2020-12-01
申请号：US16412750
申请日：2019-05-15
发明人： Suraj J. Mathew , Kris K. Brown , Raghunath Singanamalla , Vinay Nair , Fawad Ahmed , Fatma Arzum Simsek-Ege , Diem Thy N. Tran
IPC分类号： H01L27/108 , H01L29/78 , H01L29/94 , H01L27/02 , H01L27/06 , H01L49/02 , H01L29/10 , H01L23/528 , H01L29/08
摘要： Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.
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8.发明授权公开(公告)号：US10374033B1
公开(公告)日：2019-08-06
申请号：US15915158
申请日：2018-03-08
发明人： Pranav P. Sharma , Vinay Nair , Sanjeev Sapra
IPC分类号： H01L29/06 , H01L23/64 , H01L27/108 , H01L29/20 , H01L29/161
摘要： Some embodiments include an integrated assembly having a region of first semiconductor material. The region has an upper surface along a cross-section. The upper surface has a flat-topped peak and a concavity adjacent the flat-topped peak. A pillar of second semiconductor material is over the region and directly against the region. The pillar extends vertically from the upper surface. Some embodiments include a method of forming an integrated assembly. A construction is formed to have a semiconductor region, and to have an insulative region extending over the semiconductor region and alongside the semiconductor region. A combination of three etches is utilized to expose an upper surface of the semiconductor region and to modify the upper surface of the semiconductor region to form said upper surface to include, along a cross-section, a flat-topped peak portion and an adjacent concavity portion.
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公开(公告)号：US10319724B2
公开(公告)日：2019-06-11
申请号：US16033377
申请日：2018-07-12
发明人： Suraj J. Mathew , Kris K. Brown , Raghunath Singanamalla , Vinay Nair , Fawad Ahmed , Fatma Arzum Simsek-Ege , Diem Thy N. Tran
IPC分类号： H01L27/108 , H01L29/78 , H01L27/02 , H01L27/06 , H01L49/02 , H01L29/10 , H01L29/94 , H01L23/528 , H01L29/08
摘要： Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.
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公开(公告)号：US12069848B2
公开(公告)日：2024-08-20
申请号：US17729450
申请日：2022-04-26
IPC分类号： H10B12/00
CPC分类号： H10B12/482 , H10B12/485 , H10B12/50
摘要： Methods, apparatuses, and systems related to a sense line and cell contact for a semiconductor structure are described. An example apparatus includes a first source/drain region and a second source/drain region, where the first source/drain region and the second source/drain region are separated by a channel, a gate opposing the channel, a sense line material coupled to the first source/drain region by a cell contact, where the cell contact is made from a combination of a first polysilicon material and a second polysilicon material, and a storage node coupled to the second source/drain region.
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