公开(公告)号：US09412942B2

公开(公告)日：2016-08-09

申请号：US14183953

申请日：2014-02-19

Applicant: Microchip Technology Incorporated

Inventor： James Walls ,  Paul Fest

IPC: H01L45/00

CPC classification number: H01L45/1273 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1675 ,  H01L45/1691

Abstract: A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include: forming a plurality of bottom electrode connections, depositing a bottom electrode layer over the bottom electrode connections, performing a first etch to remove portions of the bottom electrode layer such that the remaining bottom electrode layer defines at least one sloped surface, forming an oxidation layer on each sloped surface of the remaining bottom electrode layer, performing a second etch on the remaining bottom electrode layer and oxidation layer on each sloped surface to define at least one upwardly-pointing bottom electrode region above each bottom electrode connection, each upwardly-pointing bottom electrode region defining a bottom electrode tip, and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top.

Abstract translation: 形成电阻式存储单元（例如CBRAM或ReRAM单元）的方法可以包括：形成多个底部电极连接，在底部电极连接上沉积底部电极层，执行第一次蚀刻以去除底部电极的部分 层，使得剩余的底部电极层限定至少一个倾斜表面，在剩余底部电极层的每个倾斜表面上形成氧化层，对每个倾斜表面上的剩余底部电极层和氧化层进行第二次蚀刻，以在 在每个底部电极连接上方的至少一个向上指向的底部电极区域，每个向上指向的底部电极区域限定底部电极尖端，以及在每个底部电极尖端上形成电解质区域和顶部电极，使得电解质区域布置在 顶部电极和相应的底部电极顶部。

公开(公告)号：US09349950B2

公开(公告)日：2016-05-24

申请号：US14183674

申请日：2014-02-19

Applicant: Microchip Technology Incorporated

Inventor： James Walls

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/142 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

Abstract: A resistive memory cell, e.g., a CBRAM or ReRAM cell, may include a top electrode, a bottom electrode having an elongated trench shape defining a pair of spaced-apart bottom electrode sidewalls, and an electrolyte switching region arranged between the top electrode and at least one of the bottom electrode sidewalls to provide a path for the formation of a conductive filament or vacancy chain from the at least one bottom electrode sidewall to the top electrode when a voltage bias is applied to the cell. In addition, a memory may include an array of resistive memory cells including a top electrode structure, a plurality of trench-style bottom electrodes extending in first direction, and a plurality of inverted-trench-style electrolyte switching regions extending perpendicular to the trench-style bottom electrodes to define a two-dimensional array of spaced-apart contact areas between the electrolyte switching regions and the bottom electrodes.

Abstract translation: 电阻式存储单元（例如CBRAM或ReRAM单元）可以包括顶电极，底电极，其具有限定一对间隔开的底电极侧壁的细长沟槽形状，以及布置在顶电极和 至少一个底部电极侧壁，以便当向电池施加电压偏压时，提供用于形成导电细丝或空位链的路径，从至少一个底部电极侧壁到顶部电极。 此外，存储器可以包括电阻存储单元的阵列，其包括顶电极结构，在第一方向上延伸的多个沟槽式底电极以及垂直于沟槽形状延伸的多个反向沟槽式电解质切换区域， 以形成在电解质切换区域和底部电极之间的间隔开的接触区域的二维阵列。

公开(公告)号：US10546947B2

公开(公告)日：2020-01-28

申请号：US16110330

申请日：2018-08-23

Applicant: Microchip Technology Incorporated

Inventor： Mel Hymas ,  Bomy Chen ,  Greg Stom ,  James Walls

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

Abstract: A method of forming a memory cell, e.g., flash memory cell, may include (a) depositing polysilicon over a substrate, (b) depositing a mask over the polysilicon, (c) etching an opening in the mask to expose a surface of the polysilicon, (d) growing a floating gate oxide at the exposed polysilicon surface, (e) depositing additional oxide above the floating gate oxide, such that the floating gate oxide and additional oxide collectively define an oxide cap, (f) removing mask material adjacent the oxide cap, (g) etching away portions of the polysilicon uncovered by the oxide cap, wherein a remaining portion of the polysilicon defines a floating gate, and (h) depositing a spacer layer over the oxide cap and floating gate. The spacer layer may includes a shielding region aligned over at least one upwardly-pointing tip region of the floating gate, which helps protect such tip region(s) from a subsequent source implant process.

公开(公告)号：US20190252395A1

公开(公告)日：2019-08-15

申请号：US15983461

申请日：2018-05-18

Applicant: Microchip Technology Incorporated

Inventor： James Walls ,  Mel Hymas ,  Sajid Kabeer

IPC: H01L27/11521 ,  H01L21/225 ,  H01L21/266 ,  H01L29/66 ,  H01L29/08 ,  H01L29/788 ,  H01L21/28

CPC classification number: H01L27/11521 ,  H01L21/2253 ,  H01L21/266 ,  H01L27/11524 ,  H01L29/0847 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7884

Abstract: A method is provided for forming an integrated circuit memory cell, e.g., flash memory cell. A pair of spaced-apart floating gate structures may be formed over a substrate. A non-conformal spacer layer may be formed over the structure, and may include spacer sidewall regions laterally adjacent the floating gate sidewalls. A source implant may be performed, e.g., via HVII, to define a source implant region in the substrate. The spacer sidewall region substantially prevents penetration of source implant material, such that the source implant region is self-aligned by the spacer sidewall region. The source implant material diffuses laterally to extend partially under the floating gate. Using the non-conformal spacer layer, including the spacer sidewall regions, may (a) protect the upper corner, or “tip” of the floating gate from rounding and (b) provide lateral control of the source junction edge location under each floating gate.

公开(公告)号：US20190206881A1

公开(公告)日：2019-07-04

申请号：US15921858

申请日：2018-03-15

Applicant: Microchip Technology Incorporated

Inventor： Mel Hymas ,  James Walls ,  Sonu Daryanani

IPC: H01L27/11517 ,  H01L27/105

Abstract: A memory cell, e.g., a flash memory cell, includes a substrate, a flat-topped floating gate formed over the substrate, and a flat-topped oxide region formed over the flat-topped floating gate. The flat-topped floating gate may have a sidewall with a generally concave shape that defines an acute angle at a top corner of the floating gate, which may improve a program or erase efficiency of the memory cell. The flat-topped floating gate and overlying oxide region may be formed with without a floating gate thermal oxidation that forms a conventional “football oxide.” A word line and a separate erase gate may be formed over the floating gate and oxide region. The erase gate may overlap the floating gate by a substantially greater distance than the word line overlaps the floating gate, which may allow the program and erase coupling to the floating gate to be optimized independently.

公开(公告)号：US20150236257A1

公开(公告)日：2015-08-20

申请号：US14184034

申请日：2014-02-19

Applicant: Microchip Technology Incorporated

Inventor： James Walls ,  Paul Fest

IPC: H01L45/00

CPC classification number: H01L45/1273 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1675

Abstract: A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include forming a plurality of bottom electrode connections, depositing a bottom electrode layer over the bottom electrode connections, performing an etch to remove portions of the bottom electrode layer to form at least one upwardly-pointing bottom electrode region above the bottom electrode connections, each upwardly-pointing bottom electrode region defining a bottom electrode tip, and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top.

Abstract translation: 形成电阻式存储单元（例如CBRAM或ReRAM单元）的方法可包括形成多个底部电极连接，在底部电极连接上沉积底部电极层，执行蚀刻以将底部电极层的部分去除 在底部电极连接部分上形成至少一个向上指向的底部电极区域，每个向上指向的底部电极区域限定底部电极尖端，并且在每个底部电极尖端上形成电解质区域和顶部电极，使得电解质区域被布置 在顶部电极和相应的底部电极顶部之间。

公开(公告)号：US20150236256A1

公开(公告)日：2015-08-20

申请号：US14183953

申请日：2014-02-19

Applicant: Microchip Technology Incorporated

Inventor： James Walls ,  Paul Fest

IPC: H01L45/00

CPC classification number: H01L45/1273 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1675 ,  H01L45/1691

Abstract: A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM cell, may include: forming a plurality of bottom electrode connections, depositing a bottom electrode layer over the bottom electrode connections, performing a first etch to remove portions of the bottom electrode layer such that the remaining bottom electrode layer defines at least one sloped surface, forming an oxidation layer on each sloped surface of the remaining bottom electrode layer, performing a second etch on the remaining bottom electrode layer and oxidation layer on each sloped surface to define at least one upwardly-pointing bottom electrode region above each bottom electrode connection, each upwardly-pointing bottom electrode region defining a bottom electrode tip, and forming an electrolyte region and a top electrode over each bottom electrode tip such that the electrolyte region is arranged between the top electrode and the respective bottom electrode top.

Abstract translation: 形成电阻式存储单元（例如CBRAM或ReRAM单元）的方法可以包括：形成多个底部电极连接，在底部电极连接上沉积底部电极层，执行第一次蚀刻以去除底部电极的部分 层，使得剩余的底部电极层限定至少一个倾斜表面，在剩余底部电极层的每个倾斜表面上形成氧化层，对每个倾斜表面上的剩余底部电极层和氧化层进行第二次蚀刻，以在 在每个底部电极连接上方的至少一个向上指向的底部电极区域，每个向上指向的底部电极区域限定底部电极尖端，以及在每个底部电极尖端上形成电解质区域和顶部电极，使得电解质区域布置在 顶部电极和相应的底部电极顶部。

公开(公告)号：US20140264245A1

公开(公告)日：2014-09-18

申请号：US14183674

申请日：2014-02-19

Applicant: Microchip Technology Incorporated

Inventor： James Walls

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/142 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

Abstract: A resistive memory cell, e.g., a CBRAM or ReRAM cell, may include a top electrode, a bottom electrode having an elongated trench shape defining a pair of spaced-apart bottom electrode sidewalls, and an electrolyte switching region arranged between the top electrode and at least one of the bottom electrode sidewalls to provide a path for the formation of a conductive filament or vacancy chain from the at least one bottom electrode sidewall to the top electrode when a voltage bias is applied to the cell. In addition, a memory may include an array of resistive memory cells including a top electrode structure, a plurality of trench-style bottom electrodes extending in first direction, and a plurality of inverted-trench-style electrolyte switching regions extending perpendicular to the trench-style bottom electrodes to define a two-dimensional array of spaced-apart contact areas between the electrolyte switching regions and the bottom electrodes.

Abstract translation: 电阻式存储单元（例如CBRAM或ReRAM单元）可以包括顶电极，底电极，其具有限定一对间隔开的底电极侧壁的细长沟槽形状，以及布置在顶电极和 至少一个底部电极侧壁，以便当向电池施加电压偏压时，提供用于形成导电细丝或空位链的路径，从至少一个底部电极侧壁到顶部电极。 此外，存储器可以包括电阻存储单元的阵列，其包括顶电极结构，在第一方向上延伸的多个沟槽式底电极以及垂直于沟槽形状延伸的多个反向沟槽式电解质切换区域， 以形成在电解质切换区域和底部电极之间的间隔开的接触区域的二维阵列。