公开(公告)号：US20200006289A1

公开(公告)日：2020-01-02

申请号：US16563919

申请日：2019-09-08

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng Chang ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Yi-Jou Lin

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package structure includes a substrate having a first surface and second surface opposite thereto, a first semiconductor die disposed on the first surface of the substrate, a second semiconductor die disposed on the first surface, a molding material surrounding the first semiconductor die and the second semiconductor die, and an annular frame mounted on the first surface of the substrate. The first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. The first semiconductor die is separated from the second semiconductor die by the molding material. The substrate includes a wiring structure. The first semiconductor die and the second semiconductor die are electrically coupled to the wiring structure. The annular frame surrounds the first semiconductor die and the second semiconductor die. The annular frame includes a retracted region at an outer corner of the annular frame.

公开(公告)号：US12183723B2

公开(公告)日：2024-12-31

申请号：US17973318

申请日：2022-10-25

Applicant: MediaTek Inc.

Inventor： Yao-Chun Su ,  Chih-Ching Chen ,  I-Hsuan Peng ,  Yi-Jou Lin

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L49/02

Abstract: A semiconductor package including at least one functional die; at least one dummy die free of active circuit, wherein the dummy die comprises at least one metal-insulator-metal (MIM) capacitor; and a redistribution layer (RDL) structure interconnecting the MIM capacitor to the at least one functional die.

公开(公告)号：US20240047427A1

公开(公告)日：2024-02-08

申请号：US18489814

申请日：2023-10-18

Applicant: MediaTek Inc.

Inventor： Yi-Lin Tsai ,  Wen-Sung Hsu ,  I-Hsuan Peng ,  Yi-Jou Lin

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L23/49822

Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor component, a conductive pillar, and a second semiconductor component. The redistribution layer is over the substrate. The first semiconductor component is over the redistribution layer. The conductive pillar is adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material. The second semiconductor component is over the molding material, wherein the second semiconductor component is electrically coupled to the redistribution layer through the conductive pillar.

公开(公告)号：US11854930B2

公开(公告)日：2023-12-26

申请号：US17901849

申请日：2022-09-01

Applicant: MEDIATEK INC.

Inventor： Yi-Lin Tsai ,  Yi-Jou Lin ,  I-Hsuan Peng ,  Wen-Sung Hsu

IPC: H01L23/48 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/3192 ,  H01L21/563 ,  H01L24/16 ,  H01L25/0655 ,  H01L2924/3511

Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A multi-layer laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.

公开(公告)号：US11469152B2

公开(公告)日：2022-10-11

申请号：US17035719

申请日：2020-09-29

Applicant: MEDIATEK INC.

Inventor： Yi-Lin Tsai ,  Yi-Jou Lin ,  I-Hsuan Peng ,  Wen-Sung Hsu

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56

Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A pre-cut laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.

公开(公告)号：US11302592B2

公开(公告)日：2022-04-12

申请号：US16217016

申请日：2018-12-11

Applicant: MEDIATEK INC.

Inventor： Chi-Wen Pan ,  I-Hsuan Peng ,  Sheng-Liang Kuo ,  Yi-Jou Lin ,  Tai-Yu Chen

IPC: H01L23/16 ,  H01L23/367 ,  H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L25/03 ,  H01L23/04 ,  H01L25/00 ,  H01L25/18 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate.

公开(公告)号：US11171113B2

公开(公告)日：2021-11-09

申请号：US16563919

申请日：2019-09-08

Applicant: MEDIATEK INC.

Inventor： Chia-Cheng Chang ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Yi-Jou Lin

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/367

Abstract: A semiconductor package structure includes a substrate having a first surface and second surface opposite thereto, a first semiconductor die disposed on the first surface of the substrate, a second semiconductor die disposed on the first surface, a molding material surrounding the first semiconductor die and the second semiconductor die, and an annular frame mounted on the first surface of the substrate. The first semiconductor die and the second semiconductor die are arranged in a side-by-side manner. The first semiconductor die is separated from the second semiconductor die by the molding material. The substrate includes a wiring structure. The first semiconductor die and the second semiconductor die are electrically coupled to the wiring structure. The annular frame surrounds the first semiconductor die and the second semiconductor die. The annular frame includes a retracted region at an outer corner of the annular frame.