公开(公告)号：US11532635B1

公开(公告)日：2022-12-20

申请号：US17346083

申请日：2021-06-11

申请人： Kepler Computing Inc.

发明人： Rajeev Kumar Dokania ,  Noriyuki Sato ,  Tanay Gosavi ,  Pratyush Pandey ,  Debo Olaosebikan ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC分类号： G11C11/22 ,  H01L27/11507 ,  H01L49/02

摘要： A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

公开(公告)号：US12034086B1

公开(公告)日：2024-07-09

申请号：US17552269

申请日：2021-12-15

申请人： Kepler Computing Inc.

发明人： Somilkumar J. Rathi ,  Noriyuki Sato ,  Niloy Mukherjee ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Tanay Gosavi ,  Pratyush Pandey ,  Jason Y. Wu ,  Sasikanth Manipatruni

IPC分类号： H10B53/30 ,  H01L21/768 ,  H01L23/522 ,  H01L29/94 ,  H01L49/02

CPC分类号： H01L29/945 ,  H01L21/76834 ,  H01L21/7687 ,  H01L21/76877 ,  H01L23/5223 ,  H01L23/5226 ,  H01L28/57 ,  H01L28/65 ,  H01L28/75 ,  H10B53/30

摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.

公开(公告)号：US11961877B1

公开(公告)日：2024-04-16

申请号：US17550899

申请日：2021-12-14

申请人： Kepler Computing Inc.

发明人： Somilkumar J. Rathi ,  Noriyuki Sato ,  Niloy Mukherjee ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Tanay Gosavi ,  Pratyush Pandey ,  Jason Y. Wu ,  Sasikanth Manipatruni

IPC分类号： H10B53/30 ,  G11C11/22 ,  H01L49/02

CPC分类号： H01L28/57 ,  H01L28/65 ,  H01L28/75 ,  H10B53/30 ,  G11C11/221

摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.

公开(公告)号：US11769790B2

公开(公告)日：2023-09-26

申请号：US17649665

申请日：2022-02-01

申请人： Kepler Computing Inc.

发明人： Niloy Mukherjee ,  Somilkumar J. Rathi ,  Jason Y. Wu ,  Pratyush Pandey ,  Zeying Ren ,  Fnu Atiquzzaman ,  Gabriel Antonio Paulius Velarde ,  Noriyuki Sato ,  Mauricio Manfrini ,  Tanay Gosavi ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Ramamoorthy Ramesh ,  Sasikanth Manipatruni

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L23/535 ,  H01L23/538 ,  H01L49/02 ,  H01L21/324 ,  H01L21/768 ,  H10B53/30 ,  H10N70/00

CPC分类号： H01L28/57 ,  H01L21/324 ,  H01L21/76832 ,  H01L28/65 ,  H01L28/75 ,  H10B53/30 ,  H10N70/8836

摘要： A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.

公开(公告)号：US20230246064A1

公开(公告)日：2023-08-03

申请号：US17649899

申请日：2022-02-03

申请人： Kepler Computing Inc.

发明人： Niloy Mukherjee ,  Somilkumar J. Rathi ,  Jason Y. Wu ,  Pratyush Pandey ,  Zeying Ren ,  FNU Atiquzzaman ,  Gabriel Antonio Paulius Velarde ,  Noriyuki Sato ,  Mauricio Manfrini ,  Tanay Gosavi ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Ramamoorthy Ramesh ,  Sasikanth Manipatruni

IPC分类号： H01L49/02 ,  H01L21/324 ,  H01L21/768 ,  H01L27/11507 ,  H01L45/00

CPC分类号： H01L28/75 ,  H01L21/324 ,  H01L21/76832 ,  H01L27/11507 ,  H01L28/57 ,  H01L28/65 ,  H01L45/147

摘要： A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.

公开(公告)号：US11605411B1

公开(公告)日：2023-03-14

申请号：US17390796

申请日：2021-07-30

申请人： Kepler Computing Inc.

发明人： Rajeev Kumar Dokania ,  Noriyuki Sato ,  Tanay Gosavi ,  Pratyush Pandey ,  Debo Olaosebikan ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC分类号： G11C11/22 ,  G11C11/417

摘要： A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

公开(公告)号：US11532342B1

公开(公告)日：2022-12-20

申请号：US17367210

申请日：2021-07-02

申请人： Kepler Computing Inc.

发明人： Rajeev Kumar Dokania ,  Noriyuki Sato ,  Tanay Gosavi ,  Pratyush Pandey ,  Debo Olaosebikan ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC分类号： G11C11/22 ,  G11C11/417

摘要： A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

公开(公告)号：US11521666B1

公开(公告)日：2022-12-06

申请号：US17346087

申请日：2021-06-11

申请人： Kepler Computing Inc.

发明人： Rajeev Kumar Dokania ,  Noriyuki Sato ,  Tanay Gosavi ,  Pratyush Pandey ,  Debo Olaosebikan ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC分类号： G11C11/22 ,  H01L27/11514 ,  H01L27/11504 ,  G11C5/10

摘要： A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

公开(公告)号：US11514966B1

公开(公告)日：2022-11-29

申请号：US17367172

申请日：2021-07-02

申请人： Kepler Computing Inc.

发明人： Rajeev Kumar Dokania ,  Noriyuki Sato ,  Tanay Gosavi ,  Pratyush Pandey ,  Debo Olaosebikan ,  Amrita Mathuriya ,  Sasikanth Manipatruni

IPC分类号： G11C11/22 ,  G11C11/417

摘要： A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.