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公开(公告)号：US20160085961A1
公开(公告)日：2016-03-24
申请号：US14824372
申请日：2015-08-12
IPC分类号： G06F21/44
CPC分类号： G06F21/44
摘要： According to an embodiment, an authentication system includes a physical device, a calculator, and an authenticator. The physical device includes a data source which outputs a data sequence along time series. The calculator performs, using hidden Markov model, probability calculation on an ID which is based on the data sequence obtained from the physical device. The authenticator authenticates the physical device based on calculation result of the calculator.
摘要翻译： 根据实施例，认证系统包括物理设备，计算器和认证器。 物理设备包括沿时间序列输出数据序列的数据源。 计算器使用隐马尔可夫模型，对基于从物理设备获得的数据序列的ID进行概率计算。 验证者根据计算器的计算结果对物理设备进行认证。
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公开(公告)号：US20150074341A1
公开(公告)日：2015-03-12
申请号：US14527373
申请日：2014-10-29
CPC分类号： G06F17/30982 , G06F12/0246 , G06F17/30097 , G06F17/3012 , G06F2212/7201
摘要： According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes an interface, a memory block, an address acquisition circuit and a controller. The interface receives a data write/read request or a request based on the key-value store. The memory block has a data area for storing data and a metadata table containing the key-value data. The address acquisition circuit acquires an address in response to input of the key. The controller executes the data write/read request for the memory block, and outputs the address acquired to the memory block and executes the request based on the key-value store. The controller outputs the value corresponding to the key via the interface.
摘要翻译： 根据一个实施例，包括密钥值存储的密钥值存储器的存储器系统包括密钥值数据作为一对密钥和对应于该密钥的值，包括接口，存储器块，地址获取电路和控制器。 接口接收数据写/读请求或基于键值存储的请求。 存储块具有用于存储数据的数据区域和包含键值数据的元数据表。 地址获取电路响应于键的输入而获取地址。 控制器执行存储器块的数据写/读请求，并将获取的地址输出到存储块，并根据键值存储执行请求。 控制器通过接口输出与该键对应的值。
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公开(公告)号：US20240143989A1
公开(公告)日：2024-05-02
申请号：US18456507
申请日：2023-08-27
摘要： A reservoir calculation device according to an embodiment includes a reservoir circuit and an output circuit. The reservoir circuit receives input data and outputs intermediate signals, each undergoing a transient change when the input data changes. The output circuit outputs an output signal obtained by combining the intermediate signals. The reservoir circuit includes intermediate circuits, each including a neuron circuit and an intermediate output circuit. The neuron circuit generates an intermediate voltage undergoing a transient change corresponding to weight data and the input data when the input data changes. The intermediate output circuit outputs an intermediate signal representing a level of the intermediate voltage from the neuron circuit. The neuron circuit includes a time constant circuit capable of changing a time constant. The time constant circuit is connected between a reference potential and an intermediate terminal outputting the intermediate voltage.
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公开(公告)号：US20210279559A1
公开(公告)日：2021-09-09
申请号：US17007331
申请日：2020-08-31
摘要： A spiking neural network device according to an embodiment includes a synaptic element, a neuron circuit, a determinator, a synaptic depressor, and a synaptic potentiator. The synaptic element has a variable weight and outputs, in response to input of a first spike signal, a synaptic signal having intensity adjusted in accordance with the weight. The neuron circuit outputs a second spike signal in a case where the synaptic signal is inputted and a predetermined firing condition for the synaptic signal is satisfied. The determinator determines whether or not the weight is to be updated on a basis of an output frequency of the second spike signal by the neuron circuit. The synaptic depressor performs depression operation for depressing the weight in a case where it is determined that the weight is to be updated. The synaptic potentiator performs potentiating operation for potentiating the weight.
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公开(公告)号：US20200293861A1
公开(公告)日：2020-09-17
申请号：US16555430
申请日：2019-08-29
发明人： Takao MARUKAME , Yoshifumi Nishi , Kumiko Nomura
摘要： According to an embodiment, an operation apparatus includes a first neural network, a second neural network, an evaluation circuit, and a coefficient-updating circuit. The first neural network performs an operation in a first mode. The second neural network performs an operation in a second mode and has a same layer structure as the first neural network. The evaluation circuit evaluates an error of the operation of the first neural network in the first mode and evaluates an error of the operation of the second neural network in the second mode. The coefficient-updating circuit updates, in the first mode, coefficients set for the second neural network based on an evaluating result of the error of the operation of the first neural network, and updates, in the second mode, coefficients set for the first neural network based on an evaluating result of the error of the operation of the second neural network.
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公开(公告)号：US20160226523A1
公开(公告)日：2016-08-04
申请号：US14924254
申请日：2015-10-27
发明人： Yoshifumi NISHI , Takao MARUKAME , Yuichiro MITANI
CPC分类号： H03M13/1131 , H03M13/1111
摘要： According to an embodiment, a decoding device includes a variable node processor, a check node processor, a first forwarder, and a second forwarder. The variable node processor is configured to perform variable node processing on variable nodes defined by a code and output first messages. The check node processor is configured to perform check node processing on check nodes defined by the code based on the first messages and output second messages. The first forwarder is configured to forward one or more first messages remaining after excluding messages to be forwarded to one or more check nodes corresponding to one or more of the second messages having been stored in ae storage, to the check nodes. The second forwarder is configured to forward the second messages to the variable nodes and forward the one or more of the second messages to the storage.
摘要翻译： 根据实施例，解码装置包括可变节点处理器，校验节点处理器，第一转发器和第二转发器。 变量节点处理器被配置为对由代码定义的变量节点执行变量节点处理并输出第一消息。 校验节点处理器被配置为基于第一消息对由代码定义的校验节点执行校验节点处理并输出第二消息。 第一转发器被配置为在将要转发的消息排除在与已经存储在存储器中的一个或多个第二消息相对应的一个或多个校验节点之后，将剩余的一个或多个第一消息转发给校验节点。 第二转发器被配置为将第二消息转发到变量节点并将一个或多个第二消息转发到存储器。
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公开(公告)号：US20160180938A1
公开(公告)日：2016-06-23
申请号：US15058828
申请日：2016-03-02
发明人： Takao MARUKAME , Kazuya MATSUZAWA , Yoshifumi NISHI , Jiezhi CHEN , Yusuke HIGASHI , Yuuichiro MITANI
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C13/0002 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C16/0408 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/26 , G11C2213/72 , G11C2213/77
摘要： According to an embodiment, a memory system includes first wiring lines; second wiring lines; third wiring lines; fourth wiring lines; and first and second storages. The first storage includes first memory cells arranged at intersections of the first wiring lines and the second wiring lines. Each of the third wiring lines is connected to any one of the first wiring lines. Each of the fourth wiring lines is pre-associated with a logical address specified by a host apparatus. The second storage includes second memory cells arranged at intersections of the third wiring lines and the fourth wiring lines. A resistance state of each of the second memory cells is set to a first resistance state or a second resistance state where a resistance value is lower than that in the first resistance state, according to a correspondence relationship between the logical address and the first wiring line.
摘要翻译： 根据实施例，存储器系统包括第一布线; 第二布线; 第三条布线; 第四条接线; 第一和第二存储。 第一存储器包括布置在第一布线和第二布线的交点处的第一存储单元。 每个第三布线连接到第一布线中的任一个。 第四布线中的每一条与由主机设备指定的逻辑地址预先关联。 第二存储器包括布置在第三布线和第四布线的交点处的第二存储单元。 根据逻辑地址和第一布线之间的对应关系，将第二存储单元中的每一个的电阻状态设置为第一电阻状态或电阻值低于第一电阻状态的第二电阻状态 。
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28.发明申请STORAGE DEVICE IN WHICH FORWARDING-FUNCTION-EQUIPPED MEMORY NODES ARE MUTUALLY CONNECTED AND DATA PROCESSING METHOD 审中-公开存储设备，其中前向功能的存储器端口被连接和数据处理方法公开(公告)号：US20160149834A1
公开(公告)日：2016-05-26
申请号：US14974245
申请日：2015-12-18
发明人： Kosuke TATSUMURA , Atsuhiro KINOSHITA , Hirotaka NISHINO , Masamichi SUZUKI , Yoshifumi NISHI , Takao MARUKAME , Takahiro KURITA
IPC分类号： H04L12/937 , H04L12/741
CPC分类号： H04L49/253 , G06F3/0605 , G06F3/0635 , G06F3/0656 , G06F3/0658 , G06F3/0683 , H04L12/6418 , H04L45/74
摘要： According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
摘要翻译： 根据一个实施例，存储设备包括多个存储器节点。 每个存储器节点包括多个输入端口，多个输出端口，选择器，分组控制器和存储器。 选择器将输入到输入端口的数据包输出输出到其中一个输出端口。 分组控制器控制选择器。 内存存储数据。 存储器节点在输入端口和输出端口相互连接。 存储器节点具有由其物理位置确定的地址。 当接收到没有寻址到具有分组控制器的存储器节点的分组时，分组控制器基于包括分组的目的地地址的信息和具有分组控制器的存储器节点的地址来切换输出分组的输出端口 。
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公开(公告)号：US20150263117A1
公开(公告)日：2015-09-17
申请号：US14484685
申请日：2014-09-12
发明人： Koichi KATO , Takao MARUKAME , Yoshifumi NISHI , Yuichiro MITANI , Takahisa KANEMURA , Kazuya OHUCHI
IPC分类号： H01L29/45 , H01L29/66 , H01L29/788 , H01L21/283 , H01L21/265
CPC分类号： H01L29/456 , H01L21/26506 , H01L21/28061 , H01L21/28512 , H01L21/28568 , H01L23/485 , H01L27/11524 , H01L27/11529 , H01L27/11543 , H01L29/0847 , H01L29/41725 , H01L29/42376 , H01L29/4925 , H01L29/4941 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to an embodiment comprises: a gate insulating film formed on a semiconductor substrate; a semiconductor layer formed on the gate insulating film; and a first metal layer formed to be electrically connected to the semiconductor layer. 1×1019 atoms/cm3 or more of a Group VI element exists in an interface of the semiconductor layer and the first metal layer.
摘要翻译： 根据实施例的半导体器件包括：形成在半导体衬底上的栅极绝缘膜; 形成在所述栅极绝缘膜上的半导体层; 以及形成为与半导体层电连接的第一金属层。 在半导体层和第一金属层的界面中存在1×10 19原子/ cm 3以上的VI族元素。
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公开(公告)号：US20140025865A1
公开(公告)日：2014-01-23
申请号：US13913708
申请日：2013-06-10
IPC分类号： G06F3/06
CPC分类号： G06F3/0679 , G06F3/0613 , G06F3/0619 , G06F3/0655 , G06F3/0656 , G06F12/0246 , G06F12/1009
摘要： According to an embodiment, a semiconductor memory device includes a controller and a second storage unit. The controller is configured to control a write process of writing data into a first storage unit in which data supplied from a host device are stored or a read process of reading the data stored in the first storage in response to a request from the host device. The second storage unit is temporarily used in the write process or the read process. The second storage unit includes a nonvolatile third storage unit having an area for storing a duplicate of the data to be written by the write process; and a nonvolatile fourth storage unit having a work area for the write process or the read process and having a higher read/write speed than the third storage unit.
摘要翻译： 根据实施例，半导体存储器件包括控制器和第二存储单元。 控制器被配置为控制将数据写入到其中存储从主机设备提供的数据的第一存储单元或响应于来自主机设备的请求读取存储在第一存储器中的数据的读取处理。 第二存储单元暂时用于写入过程或读取过程。 第二存储单元包括非易失性第三存储单元，其具有用于存储要通过写入处理写入的数据的副本的区域; 以及具有用于写入处理或读取处理并且具有比第三存储单元更高的读取/写入速度的工作区域的非易失性第四存储单元。
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