公开(公告)号：US20190179765A1

公开(公告)日：2019-06-13

申请号：US16281132

申请日：2019-02-21

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Deanna P. D. Berger ,  Michael A. Blake ,  Pak-kin Mak ,  Robert J. Sonnelitter, III ,  Guy G. Tracy ,  Chad G. Wilson

IPC: G06F12/0891 ,  G06F12/0897 ,  G06F12/0804 ,  G06F12/0864

Abstract: In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.

公开(公告)号：US20180293172A1

公开(公告)日：2018-10-11

申请号：US15479624

申请日：2017-04-05

Applicant: International Business Machines Corporation

Inventor： Michael A. Blake ,  Rebecca M. Gott ,  Pak-Kin Mak ,  Vesselina K. Papazova

IPC: G06F12/0855 ,  G06F12/0891

Abstract: Embodiments of the present invention are directed to hot cache line arbitration. An example of a computer-implemented method for hot cache line arbitration includes receiving a request for exclusive access to a cache line from a requestor of a drawer in a processing system. The method further includes bringing the cache line to a local cache of the drawer. The method further includes invalidating copies of the cache line in the processing system. The method further includes loading a remote fetch address register (RFAR) controller on other drawers in the processing system, wherein the RFAR comprises a local pending flag and a remote pending flag.

公开(公告)号：US10055355B1

公开(公告)日：2018-08-21

申请号：US15716713

申请日：2017-09-27

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Deanna P. D. Berger ,  Michael A. Blake ,  Pak-Kin Mak ,  Robert J. Sonnelitter, III ,  Guy G. Tracy ,  Chad G. Wilson

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/0804

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/0864 ,  G06F12/0897 ,  G06F2212/1024 ,  G06F2212/60

Abstract: In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.

公开(公告)号：US08874957B2

公开(公告)日：2014-10-28

申请号：US14102584

申请日：2013-12-11

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Michael A. Blake ,  Timothy C. Bronson ,  Hieu T. Huynh

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/20 ,  G06F12/08

CPC classification number: G06F11/073 ,  G06F11/0757 ,  G06F11/20 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0864 ,  G06F12/126 ,  G06F2212/1032

Abstract: A technique is provided for a cache. A cache controller accesses a set in a congruence class and determines that the set contains corrupted data based on an error being found. The cache controller determines that a delete parameter for taking the set offline is met and determines that a number of currently offline sets in the congruence class is higher than an allowable offline number threshold. The cache controller determines not to take the set in which the error was found offline based on determining that the number of currently offline sets in the congruence class is higher than the allowable offline number threshold.

公开(公告)号：US20140095926A1

公开(公告)日：2014-04-03

申请号：US14102584

申请日：2013-12-11

Applicant: International Business Machines Corporation

Inventor： Ekaterina M. Ambroladze ,  Michael A. Blake ,  Timothy C. Bronson ,  Hieu T. Huynh

IPC: G06F11/07

CPC classification number: G06F11/073 ,  G06F11/0757 ,  G06F11/20 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0864 ,  G06F12/126 ,  G06F2212/1032

Abstract: A technique is provided for a cache. A cache controller accesses a set in a congruence class and determines that the set contains corrupted data based on an error being found. The cache controller determines that a delete parameter for taking the set offline is met and determines that a number of currently offline sets in the congruence class is higher than an allowable offline number threshold. The cache controller determines not to take the set in which the error was found offline based on determining that the number of currently offline sets in the congruence class is higher than the allowable offline number threshold.

Abstract translation: 为缓存提供了一种技术。 高速缓存控制器访问同余类中的集合，并根据发现的错误确定该集合包含损坏的数据。 高速缓存控制器确定满足设置离线的删除参数，并确定同余类中当前离线集合的数量高于允许的离线号码阈值。 缓存控制器根据确定同余类中当前离线集合的数量高于允许的离线号码阈值，确定不采取脱机发生的集合。

公开(公告)号：US20130339623A1

公开(公告)日：2013-12-19

申请号：US13746882

申请日：2013-01-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ekaterina M. Ambroladze ,  Michael A. Blake ,  Timothy C. Bronson ,  Garrett M. Drapala ,  Pak-kin Mak ,  Arthur J. O'Neill

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0815 ,  G06F12/0859

Abstract: A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class.

公开(公告)号：US08560891B2

公开(公告)日：2013-10-15

申请号：US13655088

申请日：2012-10-18

Applicant: International Business Machines Corporation

Inventor： Michael A. Blake ,  Timothy C. Bronson ,  Hieu T. Huynh ,  Pak-kin Mak

IPC: G06F11/00

CPC classification number: G11C29/08 ,  G06F11/1666 ,  G06F11/20 ,  G11C11/401 ,  G11C29/883 ,  G11C2029/0401

Abstract: A computer implemented method of embedded dynamic random access memory (EDRAM) macro disablement. The method includes isolating an EDRAM macro of a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows. Each line of the EDRAM macro is iteratively tested, the testing including attempting at least one write operation at each line of the EDRAM macro. It is determined that an error occurred during the testing. Write perations for an entire row of EDRAM macros associated with the EDRAM macro are disabled based on the determining.

Abstract translation: 嵌入式动态随机存取存储器（EDRAM）宏禁用的计算机实现方法。 该方法包括隔离高速缓存存储体的EDRAM宏，该高速缓存存储体被划分成多个EDRAM宏的至少三行，该EDRAM宏与至少三行之一相关联。 EDRAM宏的每一行被迭代测试，测试包括尝试在EDRAM宏的每一行进行至少一次写入操作。 确定在测试期间发生错误。 基于确定，禁用与EDRAM宏相关联的整行EDRAM宏的写入。

公开(公告)号：US20200285592A1

公开(公告)日：2020-09-10

申请号：US16292762

申请日：2019-03-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ekaterina M. Ambroladze ,  Robert J. Sonnelitter, III ,  Matthias Klein ,  Craig Walters ,  Kevin Lopes ,  Michael A. Blake ,  Tim Bronson ,  Kenneth Klapproth ,  Vesselina Papazova ,  Hieu T Huynh

IPC: G06F12/126 ,  G06F12/0811 ,  G06F12/084

Abstract: Embodiments of the present invention are directed to a computer-implemented method for cache eviction. The method includes detecting a first data in a shared cache and a first cache in response to a request by a first processor. The first data is determined to have a mid-level cache eviction priority. A request is detected from a second processor for a same first data as requested by the first processor. However, in this instance, the second processor has indicated that the same first data has a low-level cache eviction priority. The first data is duplicated and loaded to a second cache, however, the data has a low-level cache eviction priority at the second cache.

公开(公告)号：US20180365070A1

公开(公告)日：2018-12-20

申请号：US15625674

申请日：2017-06-16

Applicant: International Business Machines Corporation

Inventor： Michael A. Blake ,  Mike Chow ,  Kenneth D. Klapproth ,  Pak-kin Mak ,  Arthur J. O'Neill, JR. ,  Robert J. Sonnelitter, III

IPC: G06F9/50 ,  G06F11/34 ,  G06F11/30

Abstract: Methods, systems, and computer program products for managing broadcasts in a distributed symmetric multiprocessing computer are provided. Aspects include defining a default broadcast rate for a plurality of processors in the distributed symmetric multiprocessing computer, wherein the default broadcast rate is a rate at which a processor broadcasts a request for a resource. The one or more broadcasted requests by a first processor are monitored and related responses are utilized to determine a state of the one or more broadcasted requests. The default broadcast rate is adjusted based at least in part on the state of the one or more broadcasted requests.

公开(公告)号：US20180341587A1

公开(公告)日：2018-11-29

申请号：US15800369

申请日：2017-11-01

Applicant: International Business Machines Corporation

Inventor： Michael A. Blake ,  Timothy C. Bronson ,  Pak-kin Mak ,  Vesselina K. Papazova ,  Robert J. Sonnelitter, III

IPC: G06F12/084 ,  G06F12/0862

Abstract: Embodiments of the present invention are directed to managing a shared high-level cache for dual clusters of fully connected integrated circuit multiprocessors. An example of a computer-implemented method includes: providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors; providing a shared cache integrated circuit to manage a shared cache memory among the plurality of clusters; receiving, by the shared cache integrated circuit, an operation of one of a plurality of operation types from one of the plurality of processors; and processing, by the shared cache integrated circuit, the operation based at least in part on the operation type of the operation according to a set of rules for processing the operation type.