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37 条记录 (耗时 0.024 秒)

    MOS output buffer with overvoltage protection circuitry
    21.
    发明授权
    MOS output buffer with overvoltage protection circuitry 有权
    MOS输出缓冲器带过压保护电路

    公开(公告)号：US06249146B1

    公开(公告)日：2001-06-19

    申请号：US09523951

    申请日：2000-03-13

    申请人： Hiroshi Shigehara ,  Masanori Kinugasa

    发明人： Hiroshi Shigehara ,  Masanori Kinugasa

    IPC分类号： H03K190175

    CPC分类号： H03K19/00315

    摘要： Either the power-supply potential or a ground potential is applied to a power-supply node through a switch. When a potential higher than the ground potential is applied to the output terminal while an power-supply node is connected to the ground-potential node, the potential of a back gate of a first PMOS transistor incorporated in an output section increases in accordance with the potential of the output terminal, due to the pn-junction provided between a drain and back gate of the first PMOS transistor. At this time, a second PMOS transistor whose source-drain path is connected between the back gate and gate of the first PMOS transistor is turned on, whereby the potential of the back gate of the first PMOS transistor is transferred to the gate thereof.

    摘要翻译： 电源电位或接地电位通过开关施加到电源节点。 当电源节点连接到接地电位节点时，将高于接地电位的电位施加到输出端子时，结合在输出部分中的第一PMOS晶体管的背栅极的电位根据 由于设置在第一PMOS晶体管的漏极和背栅之间的pn结，输出端子的电位。 此时，源极 - 漏极路径连接在第一PMOS晶体管的背栅极和栅极之间的第二PMOS晶体管导通，由此第一PMOS晶体管的背栅极的电位被传送到其栅极。

    Auto-clear circuit and integrated circuit including an auto-clear circuit for initialization based on a power supply voltage
    22.
    发明授权
    Auto-clear circuit and integrated circuit including an auto-clear circuit for initialization based on a power supply voltage 失效
    自动清除电路和集成电路，包括基于电源电压进行初始化的自动清除电路

    公开(公告)号：US5825220A

    公开(公告)日：1998-10-20

    申请号：US778743

    申请日：1997-01-02

    申请人： Masanori Kinugasa ,  Hiroshi Shigehara ,  Akira Takiba

    发明人： Masanori Kinugasa ,  Hiroshi Shigehara ,  Akira Takiba

    IPC分类号： H03K3/356 ,  H03K17/22

    CPC分类号： H03K3/356008 ,  H03K17/223

    摘要： An auto-clear circuit which has a switch device connected between a power supply voltage terminal and first and second nodes, and a potential division device, connected between the first node and a ground terminal, for outputting a first potential obtained by dividing a potential of the first node. Also included is a charge/discharge device, connected between the second node and a ground terminal, for charging or discharging the second node on the basis of the first potential output from the potential division device, and a latch device for holding a potential of the second node to output a signal from an output terminal, and supplying the signal to the switch device to control an opening/closing operation.

    摘要翻译： 一种自动清除电路，其具有连接在电源电压端子和第一和第二节点之间的开关装置，以及连接在第一节点和接地端子之间的电位分配装置，用于输出通过将第一电位除以 第一个节点。 还包括连接在第二节点和接地端子之间的充电/放电装置，用于基于来自电势分配装置的第一电位输出对第二节点进行充电或放电;以及锁存装置，用于保持电位 第二节点输出来自输出端子的信号，并将信号提供给开关装置以控制开/关操作。

    Output buffer circuit
    23.
    发明授权
    Output buffer circuit 失效
    输出缓冲电路

    公开(公告)号：US5321326A

    公开(公告)日：1994-06-14

    申请号：US875655

    申请日：1992-04-29

    申请人： Hiroshi Shigehara ,  Masanori Kinugasa

    发明人： Hiroshi Shigehara ,  Masanori Kinugasa

    IPC分类号： H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175

    CPC分类号： H03K19/00361

    摘要： An output buffer circuit includes a first output buffer having a high output resistance determined by DC specifications, a second output buffer having an output resistance satisfying AC specifications when simultaneously driven with the first output buffer, and a control circuit for controlling an operation of the second output buffer. An input signal is supplied to the input node of the first output buffer, and the output node of the first output buffer is connected to an output terminal. The output node of the second output buffer is connected to the output terminal. The control circuit is responsive to the potential of the input signal or of the output terminal to control the operation of the second output buffer. The control circuit drives the second output buffer when the output from the first output buffer is changed, and sets the output from the second output buffer in the high impedance state when the output from the first output buffer is stationary.

    摘要翻译： 输出缓冲电路包括具有由DC规格确定的高输出电阻的第一输出缓冲器，当与第一输出缓冲器同时驱动时具有满足AC规格的输出电阻的第二输出缓冲器，以及用于控制第二输出缓冲器的操作的控制电路 输出缓冲区。 输入信号被提供给第一输出缓冲器的输入节点，第一输出缓冲器的输出节点连接到输出端。 第二输出缓冲器的输出节点连接到输出端子。 控制电路响应于输入信号或输出端子的电位来控制第二输出缓冲器的操作。 当来自第一输出缓冲器的输出改变时，控制电路驱动第二输出缓冲器，并且当来自第一输出缓冲器的输出静止时，将来自第二输出缓冲器的输出设置为高阻抗状态。

    Analog switch circuit
    24.
    发明授权
    Analog switch circuit 有权
    模拟开关电路

    公开(公告)号：US06828846B2

    公开(公告)日：2004-12-07

    申请号：US10300807

    申请日：2002-11-21

    申请人： Takumi Tsukazaki ,  Masato Fukuoka ,  Masanori Kinugasa

    发明人： Takumi Tsukazaki ,  Masato Fukuoka ,  Masanori Kinugasa

    IPC分类号： H03K1762

    CPC分类号： H03K17/6874 ,  H03K17/165 ,  H03K17/6872 ,  H03K2217/0018

    摘要： An analog switch circuit includes: an analog switch composed of a first P-channel MOS transistor and a first N-channel transistor, a gate of which receives a control signal; a comparison circuit comparing potentials of a first input-output-terminal and a second input-output terminal, and conveying a higher potential to a well where the first P-channel MOS transistor is formed; a first potential conveying circuit conveying a potential of the well where the first P-channel MOS transistor is formed to a gate of the first P-channel MOS transistor when the analog switch is in the OFF state; a second potential conveying circuit operating on the basis of a control signal to convey the potential of the well where the first P-channel MOS transistor is formed to the gate of the first P-channel MOS transistor to turn off the first P-channel MOS transistor; and a third potential conveying section operating on the basis of the control signal to turn on the first P-channel MOS transistor.

    摘要翻译： 模拟开关电路包括：由第一P沟道MOS晶体管和第一N沟道晶体管构成的模拟开关，其栅极接收控制信号; 比较电路，比较第一输入 - 输出端和第二输入 - 输出端的电位，并向形成第一P沟道MOS晶体管的阱传送更高的电位; 当所述模拟开关处于截止状态时，将形成所述第一P沟道MOS晶体管的阱的电势传送到所述第一P沟道MOS晶体管的栅极的第一潜在输送电路; 基于控制信号操作的第二电位传送电路，以将形成有第一P沟道MOS晶体管的阱的电位传送到第一P沟道MOS晶体管的栅极，以将第一P沟道MOS 晶体管 以及第三电位输送部，其基于所述控制信号进行工作，以导通所述第一P沟道MOS晶体管。

    Protection circuit for semiconductor devices
    27.
    发明授权
    Protection circuit for semiconductor devices 失效
    半导体器件保护电路

    公开(公告)号：US5821797A

    公开(公告)日：1998-10-13

    申请号：US623838

    申请日：1996-03-29

    申请人： Masanori Kinugasa ,  Ryuji Fujiwara

    发明人： Masanori Kinugasa ,  Ryuji Fujiwara

    IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L23/58 ,  H01L27/02 ,  H01L27/088 ,  H03K17/16

    CPC分类号： H01L27/0251

    摘要： A protection circuit (1) for input comprises two transistors (11, 12) connected in series between a first voltage supply (V.sub.cc) and a second voltage supply (GND), and an intermediate junction point is used as an input terminal and an output terminal. When a surge voltage is applied to the input terminal, since terminals (51, 53) of the two transistors (11, 12) are connected to predetermined junction points in such a way that the transistors can operate as bipolar transistors or cause punch through phenomenon (without causing breakdown operation of a low response speed to surge voltage), the surge voltage can be absorbed at high speed, thus increasing anti-ESD (electro static discharge) rate. Further, a protection circuit for power supply comprises two transistors (31, 32) connected in parallel to each other between a first voltage supply (V.sub.cc) and a second voltage supply (GND). Similarly, the terminals (65, 68) of the two transistors are connected to predetermined junction points in such a way that when a surge voltage is superimposed upon the supply voltage, at least one of the transistors can operate as a bipolar transistor, without causing breakdown operation.

    摘要翻译： 用于输入的保护电路（1）包括串联连接在第一电压源（Vcc）和第二电压源（GND）之间的两个晶体管（11,12），并且中间连接点用作输入端子和输出端 终奌站。 当浪涌电压施加到输入端时，由于两个晶体管（11,12）的端子（51,53）连接到预定的连接点，晶体管可以作为双极晶体管工作或引起冲击现象 （不引起低响应速度对浪涌电压的击穿操作），浪涌电压可以高速吸收，从而增加抗静电（静电放电）率。 此外，用于电源的保护电路包括在第一电压源（Vcc）和第二电压源（GND）之间并联连接的两个晶体管（31,32）。 类似地，两个晶体管的端子（65,68）以这样的方式连接到预定的接合点，使得当浪涌电压叠加在电源电压上时，至少一个晶体管可以作为双极晶体管工作，而不会引起 击穿操作。

    Semiconductor device having a multilayered wiring structure
    28.
    发明授权
    Semiconductor device having a multilayered wiring structure 失效
    具有多层布线结构的半导体器件

    公开(公告)号：US5402005A

    公开(公告)日：1995-03-28

    申请号：US291037

    申请日：1994-08-15

    申请人： Kohichi Takayama ,  Masanori Kinugasa ,  Munenobu Kida ,  Shuichi Shoji

    发明人： Kohichi Takayama ,  Masanori Kinugasa ,  Munenobu Kida ,  Shuichi Shoji

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48 ,  H01L29/46 ,  H01L29/54 ,  H01L29/62

    CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L2924/0002

    摘要： At least one slit having a predetermined shape is formed around a contact region of a lower wiring layer formed on a substrate, and an insulating portion formed integrally with an insulating layer is embedded in this slit. This insulating layer is formed on the lower wiring layer and has a contact hole located at a position corresponding to the contact region. Since the insulating portion as a rectangular projecting portion projects into the slit downwardly from the rigid insulating layer, positional errors caused by thermal expansion of the lower wiring layer in annealing of the upper wiring layer can be suppressed, and an abnormal geometry such as a projection on the upper wiring layer can be prevented. In addition, a semiconductor device free from interwiring short-circuiting and excellent in flatness can be obtained.

    摘要翻译： 在形成在基板上的下布线层的接触区域周围形成具有预定形状的至少一个狭缝，并且与该绝缘层一体形成的绝缘部分嵌入该狭缝中。 该绝缘层形成在下布线层上，并具有位于与接触区域对应的位置的接触孔。 由于作为矩形突起部分的绝缘部分从刚性绝缘层向下突出到狭缝中，所以可以抑制由上部布线层的退火中的下部布线层的热膨胀引起的位置误差，以及诸如突起 可以防止在上部布线层上。 此外，可以获得没有相互连接短路并且具有优异的平坦度的半导体器件。

    Protection circuit provided in semiconductor circuit
    29.
    发明授权
    Protection circuit provided in semiconductor circuit 失效
    半导体电路中提供的保护电路

    公开(公告)号：US06762460B2

    公开(公告)日：2004-07-13

    申请号：US09983124

    申请日：2001-10-23

    申请人： Akira Takiba ,  Masanori Kinugasa ,  Yoshimitsu Itoh ,  Masaru Mizuta

    发明人： Akira Takiba ,  Masanori Kinugasa ,  Yoshimitsu Itoh ,  Masaru Mizuta

    IPC分类号： H01L2362

    CPC分类号： H01L27/0266

    摘要： A protection circuit including a power supply terminal supplied with a power supply potential, a reference terminal supplied with a reference potential, and a first p-channel MOS transistor having a first gate, a first source, a first drain and a first back gate. The first gate, the first source and the first back gate are connected to the power supply terminal. Also included is a second p-channel MOS transistor having a second gate, a second source, a second drain and the first back gate, in which the second source of the second p-channel MOS transistor is connected to the first drain of the first p-channel MOS transistor, and the second gate and the second drain of the second p-channel MOS transistor is connected to the reference terminal. The circuit also includes a first n-channel MOS transistor having a third gate, a third source, a third drain and a second back gate, in which the third gate, in which the third source and the second back gate of the first n-channel MOS transistor are connected to the reference terminal, and including a second n-channel MOS transistor having a fourth gate, a fourth source, a fourth drain and the second back gate, in which the fourth source of the second n-channel MOS transistor are connected to the third drain of the first n-channel MOS transistor, and the fourth gate and the fourth drain of the second n-channel MOS transistor are connected to the power supply terminal.

    摘要翻译： 一种保护电路，包括供电电源的电源端子，提供有参考电位的基准端子以及具有第一栅极，第一源极，第一漏极和第一后栅极的第一p沟道MOS晶体管。 第一栅极，第一源极和第一后栅极连接到电源端子。 还包括具有第二栅极，第二源极，第二漏极和第一后栅极的第二p沟道MOS晶体管，其中第二P沟道MOS晶体管的第二源极连接到第一栅极 p沟道MOS晶体管，第二p沟道MOS晶体管的第二栅极和第二漏极连接到参考端子。 该电路还包括具有第三栅极，第三源极，第三漏极和第二后栅极的第一n沟道MOS晶体管，其中第三栅极，其中第一栅极，第三漏极和第二栅极的第三源极和第二反向栅极， 沟道MOS晶体管连接到参考端，并且包括具有第四栅极，第四源极，第四漏极和第二后栅极的第二n沟道MOS晶体管，其中第二n沟道MOS晶体管的第四源极 连接到第一n沟道MOS晶体管的第三漏极，第二n沟道MOS晶体管的第四栅极和第四漏极连接到电源端子。

    Temperature detector circuit having function for restricting occurrence of output error caused by dispersion in element manufacture
    30.
    发明授权
    Temperature detector circuit having function for restricting occurrence of output error caused by dispersion in element manufacture 失效
    温度检测电路具有限制元件制造中色散引起的输出误差的发生的功能

    公开(公告)号：US06337603B1

    公开(公告)日：2002-01-08

    申请号：US09606016

    申请日：2000-06-29

    申请人： Masanori Kinugasa ,  Yoshimitsu Itoh ,  Masaru Mizuta ,  Akira Takiba ,  Shinji Inada

    发明人： Masanori Kinugasa ,  Yoshimitsu Itoh ,  Masaru Mizuta ,  Akira Takiba ,  Shinji Inada

    IPC分类号： H03B504

    CPC分类号： H03B5/04 ,  H03B5/36

    摘要： A temperature detector circuit for converting a forward drop voltage of a diode to digital data by means of an AD converter is provided. In order to restrict an occurrence of an output error caused by dispersion in diode manufacture, correction data according to digital data obtained by the AD converter is stored in advance in a storage circuit under a known arbitrary temperature condition, and subtraction is performed between digital data obtained by the AD converter under an unknown temperature condition and correction data read from a storage circuit, thereby to perform correction.

    摘要翻译： 提供一种用于通过AD转换器将二极管的正向压降电压转换为数字数据的温度检测器电路。 为了限制二极管制造中由色散引起的输出误差的发生，根据AD转换器获得的数字数据的校正数据预先存储在已知的任意温度条件下的存储电路中，并且在数字数据 在未知温度条件下由AD转换器获得的校正数据和从存储电路读取的校正数据，从而进行校正。