公开(公告)号：US5111451A

公开(公告)日：1992-05-05

申请号：US429213

申请日：1989-10-27

Applicant: Douglas S. Piasecki ,  Eric J. Swanson ,  Russell A. Hershbarger

Inventor： Douglas S. Piasecki ,  Eric J. Swanson ,  Russell A. Hershbarger

IPC: H04L5/14

CPC classification number: H04L5/1492

Abstract: An optical communication system includes two optical modems (12) and (14) which are disposed at either end of an optical fiber data link (10). The optical modems (12) and (14) communicate through LEDs (16) and (18), respectively, with the fiber data link (10). Each of the optical modems (12) and (14) on start-up are peerless and do not operate in either a master or a slave configuration. A ping-pong transmission format is utilized with transmitted packets of data. When one of the optical modems (12) or (14) detects a transmitted packet from the other, it locks up to the transmitted packet with a phase lock loop and takes on slave status. This slave status is transmitted back to the fiber data link (10) in another transmitted packet. The transmitted packet from the slave device is then adjusted time relative to the machine cycle of the slave device until the packet is received by the other optical modem. Once the other optical modem receives the transmitted packet from the slave optical modem, it recognizes this fact and takes on a master status. This master status is transmitted back to the slave optical modem and adjustment of the relative position of the transmitted packet therein is terminated and the start-up procedure is terminated.

Abstract translation: 光通信系统包括设置在光纤数据链路（10）的任一端的两个光调制解调器（12）和（14）。 光调制解调器（12）和（14）分别与光纤数据链路（10）通过LED（16）和（18）通信。 启动时的每个光调制解调器（12）和（14）都是无与伦比的，不能在主器件或从器件中工作。 传输的数据包使用乒乓传输格式。 当光调制解调器（12）或（14）中的一个从另一个调制解调器（12）或（14）检测到发送的分组时，它锁定到具有锁相环的所发送的分组，并且进行从属状态。 该从属状态在另一个发送的分组中传送回光纤数据链路（10）。 然后从从设备发送的分组相对于从设备的机器周期来调整时间，直到分组被另一个光调制解调器接收。 一旦另一个光学调制解调器从从属光调制解调器接收到发送的数据包，它就会识别这一事实并承担主器件状态。 该主状态被发回到从属光调制解调器，并且其中发送的分组的相对位置的调整被终止，并且终止启动过程。

公开(公告)号：US5088107A

公开(公告)日：1992-02-11

申请号：US429225

申请日：1989-10-27

Applicant: Douglas S. Piasecki ,  Eric J. Swanson

Inventor： Douglas S. Piasecki ,  Eric J. Swanson

IPC: H04B10/158

CPC classification number: H04B10/6932

Abstract: A calibration circuit for a linear channel of an optical modem includes circuitry interconnected to the linear channel for causing the linear channel to oscillate. Circuitry is interconnected to the output of the linear channel for monitoring the bandwidth of the linear channel during oscillation and for generating output pulses. The output pulses are counted and are utilized for generating an adjustment signal applied to the linear channel for adjusting the bandwidth of the linear channel.

Abstract translation: 用于光调制解调器的线性通道的校准电路包括互连到线性通道的电路，用于使线性通道振荡。 电路与线性通道的输出互连，用于在振荡期间监视线性通道的带宽并产生输出脉冲。 对输出脉冲进行计数，并用于产生施加到线性通道的调整信号，以调整线性通道的带宽。

公开(公告)号：US5068660A

公开(公告)日：1991-11-26

申请号：US428397

申请日：1989-10-27

Applicant: Eric J. Swanson ,  Bruce P. Del Signore

Inventor： Eric J. Swanson ,  Bruce P. Del Signore

IPC: H03M3/02

CPC classification number: H03M3/376 ,  H03M3/43 ,  H03M3/438

Abstract: An oversampling analog-to-digital modulator includes an analog loop filter which has a first integrator stage which is a single-ended integrator. The second, third, and fourth integrator stages are fully-differential integrators. The first integrator provides the required thermal noise characteristics of the loop filter with only one feedback capacitor which is external to the integrated circuit chip, while the fully-differential integrator stages provide improved suppression of charge injection transients.

Abstract translation: 过采样模数转换器包括模拟环路滤波器，其具有作为单端积分器的第一积分器级。 第二，第三和第四个积分器级是全差分积分器。 第一个积分器提供了环路滤波器所需的热噪声特性，只有一个集成电路芯片外部的反馈电容器，而全差分积分器级提供了电荷注入瞬变的改进抑制。

公开(公告)号：US5061925A

公开(公告)日：1991-10-29

申请号：US571376

申请日：1990-08-22

Applicant: Navdeep S. Sooch ,  Donald A. Kerth ,  Eric J. Swanson ,  Tetsurou Sugimoto

Inventor： Navdeep S. Sooch ,  Donald A. Kerth ,  Eric J. Swanson ,  Tetsurou Sugimoto

IPC: H03M1/66 ,  H03H17/00 ,  H03H17/02 ,  H03H17/06 ,  H03M3/02 ,  H03M7/00 ,  H03M7/32

CPC classification number: H03M3/37 ,  H03M3/50 ,  H03M7/3028 ,  H03M7/3035 ,  H03M7/3037

Abstract: A phase equalization system for a digital-to-analog converter (DAC) includes a digital portion (10) having an interpolation section (14) for receiving a digital input and increasing the sampling frequency thereof for input to a delta-sigma modulator (16). A summing junction (24) is disposed between the interpolation circuit (14) and the delta-sigma modudlator (16) to allow an offset voltage to be summed therewith. This provides for D.C. offset, this offset being controlled by a calibration control (40). The output of the digital section (10) is input in an analog section (12), which has a one-bit DAC 21) that is input to an analog filter (22) for converting and filtering the one-bit digital stream output by the delta-sigma modulator (16). The interpolation circuit (14) includes a three stage interpolation filter comprising a first stage (50), a second stage (52) and a third stage (54). The second stage (52) is comprised of a finite impulse response filter (FIR) that has a nonlinear phase response. The nonlinear phase response of the interpolation filter (52) compensates for the phase deviation of the analog filter (22) from a linear phase response. Therefore, the composite phase provided by the combination of the phase equalization in the digital section (10) and the phase nonlinearity in the analog section (12) will result in a linear overall phase relationship for the DAC.

Abstract translation: 用于数模转换器（DAC）的相位均衡系统包括具有插值部分（14）的数字部分（10），用于接收数字输入并增加其采样频率以输入到Δ-Σ调制器（16 ）。 在插值电路（14）和Δ-Σ调制器（16）之间设置加法结（24），以允许偏移电压与其相加。 这提供直流偏移，该偏移由校准控制（40）控制。 数字部分（10）的输出被输入到模拟部分（12）中，模拟部分（12）具有一个比特DAC21），该模拟部分（12）被输入到模拟滤波器（22），用于转换和滤波由 Δ-Σ调制器（16）。 内插电路（14）包括三级内插滤波器，包括第一级（50），第二级（52）和第三级（54）。 第二级（52）由具有非线性相位响应的有限脉冲响应滤波器（FIR）组成。 内插滤波器（52）的非线性相位响应补偿模拟滤波器（22）与线性相位响应的相位偏差。 因此，通过数字部分（10）中的相位均衡和模拟部分（12）中的相位非线性的组合提供的复合相位将导致DAC的线性整体相位关系。

公开(公告)号：US4849662A

公开(公告)日：1989-07-18

申请号：US851805

申请日：1986-04-14

Applicant: Douglas R. Holberg ,  Eric J. Swanson

Inventor： Douglas R. Holberg ,  Eric J. Swanson

IPC: H03H19/00 ,  H03H15/02 ,  H03H9/64

CPC classification number: H03H19/00

Abstract: A method and circuitry for time-sharing a digitally-programmable capacitive element, particularly in conjunction with a switched-capacitor filter circuit. The method includes: selecting a first capacitance value for the capacitive element; initializing the charge on the capacitive element; connecting the capacitive element to first preselected nodes of an electronic circuit; disconnecting the capacitive element from the first preselected nodes of after any charge transfer has substantially been completed; changing the capacitance of the capacitive element to a new desired value; initializing the charge on the capacitive element; and then connecting the capacitive element to other preselected nodes of the electronic circuit. A biquad switched-capacitor filter circuit is configured to use such method in its operation.

公开(公告)号：US4570080A

公开(公告)日：1986-02-11

申请号：US540277

申请日：1983-10-11

Applicant: Eric J. Swanson

Inventor： Eric J. Swanson

IPC: G11C27/02 ,  H03K17/14

CPC classification number: G11C27/026

Abstract: An electronic sample-and-hold circuit (10, 24) of the type which includes a correction network is designed to eliminate a primary signal feedback loop. A correction capacitor, (C.sub.C), a coupling capacitor (C.sub.CC), and a primary holding capacitor (C.sub.H) are connected in series, respectively, between two ground points. The common node of the coupling capacitor and the holding capacitor is a held signal node (12). The common node of the coupling capacitor (C.sub.CC) and the correction capacitor (C.sub.C) is a correction voltage node (20). The circuit output is from the signal node (12) through a buffer (14) and a stage selecting switch (S.sub.F). The output is fed back to an operational amplifier (18, 26) which has its output connected to the correction node (20) through a correction sampling switch (S.sub.C). A switched (S.sub.A) feedback loop connects the output of the amplifier 18 to the inverting input port. The primary signal input (IN) is to the signal node (12) through a primary sampling switch (S.sub.S). The noninverting input (+) of the amplifier (26) is connected to the output of a buffer (22). The input of the buffer (22) receives the input signal through an input switch (S.sub.I) and is also connected to an input capacitor (C.sub.I), which has its other side grounded.Also disclosed is a circuit (24) in which the operational amplifier (26) is a less complex, inverting amplifier provided with a switched (S.sub.A) local bypass loop.

Abstract translation: 包括校正网络的电子采样保持电路（10,24）被设计为消除主信号反馈回路。 分别在两个接地点之间串联连接有校正电容器（CC），耦合电容器（CCC）和初级保持电容器（CH）。 耦合电容器和保持电容器的公共节点是保持信号节点（12）。 耦合电容器（CCC）和校正电容器（CC）的公共节点是校正电压节点（20）。 电路输出来自信号节点（12）通过缓冲器（14）和级选择开关（SF）。 输出被反馈到运算放大器（18,26），运算放大器的输出通过校正采样开关（SC）连接到校正节点（20）。 开关（SA）反馈环路将放大器18的输出连接到反相输入端口。 主信号输入（IN）通过主采样开关（SS）传送到信号节点（12）。 放大器（26）的同相输入（+）连接到缓冲器（22）的输出端。 缓冲器（22）的输入通过输入开关（SI）接收输入信号，并且还连接到另一侧接地的输入电容器（CI）。 还公开了一种电路（24），其中运算放大器（26）是具有开关（SA）局部旁路回路的较不复杂的反相放大器。

公开(公告)号：US08525710B1

公开(公告)日：2013-09-03

申请号：US12750973

申请日：2010-03-31

Applicant: Robin Matthew Tsang ,  Eric J. Swanson ,  John L. Melanson ,  John Christopher Tucker

Inventor： Robin Matthew Tsang ,  Eric J. Swanson ,  John L. Melanson ,  John Christopher Tucker

IPC: H03M1/06 ,  H03M1/66 ,  H03F99/00

CPC classification number: H03M1/0607 ,  H03F3/45475 ,  H03F3/45968 ,  H03F2203/45522 ,  H03F2203/45528 ,  H03M1/66 ,  H03M3/50

Abstract: An offset correction circuit removes DC offset from an analog audio output signal by comparing transitions of digital audio values to which the analog output signal is related to the output of a monitor that monitors the analog output signal. The monitor may be a zero-crossing detector and the transitions of the digital signal that are compared may be transitions of the most-significant bit (MSB) of the digital audio values. A filtering algorithm or filter circuit may be used to average a result of the comparison of the transitions, so that the offset is slowly and accurately removed. A chopped or autozero comparator may be used to further reduce error in the offset determination.

Abstract translation: 偏移校正电路通过比较模拟输出信号与监视模拟输出信号的监视器的输出相关的数字音频值的转换，从模拟音频输出信号中去除DC偏移。 监视器可以是过零检测器，并且被比较的数字信号的转变可以是数字音频值的最高有效位（MSB）的转换。 可以使用滤波算法或滤波器电路来平均转换的比较的结果，使得偏移被缓慢且精确地去除。 可以使用斩波或自动调零比较器来进一步减少偏移确定中的误差。

公开(公告)号：US07808324B1

公开(公告)日：2010-10-05

申请号：US12405485

申请日：2009-03-17

Applicant: Scott Allan Woodford ,  Daniel John Allen ,  Eric J. Swanson

Inventor： Scott Allan Woodford ,  Daniel John Allen ,  Eric J. Swanson

IPC: H03F3/04

CPC classification number: H03F3/21 ,  H03F3/185 ,  H03F2200/468

Abstract: A charge pump power supply for an audio power amplifier integrated circuit has an operating mode selected according to an indication of operating environment and/or a process position of the integrated circuit. The operating mode selects the output voltage provided by the charge pump and may also select efficiency by selecting a frequency of operation of the charge pump and/or the effective size of a switching transistor bank. The selection is made in conformity with an indication of a process position of the integrated circuit and/or an indication of an environment of the integrated circuit, such as temperature, power supply voltage and/or load impedance values, and generally also in conformity with a volume (gain) setting, or a detected signal level, so that internal power consumption of the amplifier and charge pump is reduced when a high signal level is not being reproduced at the audio power stage.

Abstract translation: 用于音频功率放大器集成电路的电荷泵电源具有根据操作环境的指示和/或集成电路的处理位置选择的操作模式。 操作模式选择由电荷泵提供的输出电压，还可以通过选择电荷泵的工作频率和/或开关晶体管组的有效尺寸来选择效率。 选择符合集成电路的处理位置的指示和/或集成电路的环境的指示，例如温度，电源电压和/或负载阻抗值，并且通常也符合 音量（增益）设置或检测到的信号电平，使得当在音频功率级不再现高信号电平时，放大器和电荷泵的内部功耗降低。

公开(公告)号：US07746257B2

公开(公告)日：2010-06-29

申请号：US12366214

申请日：2009-02-05

Applicant: Edmund M. Schneider ,  Eric J. Swanson ,  John L. Melanson

Inventor： Edmund M. Schneider ,  Eric J. Swanson ,  John L. Melanson

IPC: H03M3/00

CPC classification number: H03M3/428 ,  H03M3/368 ,  H03M3/414 ,  H03M3/456

Abstract: A delta-sigma analog-to-digital converter (ADC) circuit improves performance by reducing the amount of noise and other error sampled by the reference switching circuit. The reference switching network is operated intermittently only when the charge on an input integrator exceeds a threshold, thereby preventing the input integrator from saturating, while avoiding needlessly injecting reference noise. The input to the ADC may be a current injected directly into a summing node of the integrator, or may be a voltage supplied through another switching network.

Abstract translation: Δ-Σ模数转换器（ADC）电路通过减少由参考开关电路采样的噪声和其他误差来提高性能。 仅当输入积分器上的电荷超过阈值时，参考开关网络间歇运行，从而防止输入积分器饱和，同时避免不必要地注入参考噪声。 ADC的输入可以是直接注入到积分器的求和节点中的电流，或者可以是通过另一个交换网络提供的电压。

公开(公告)号：US06392580B1

公开(公告)日：2002-05-21

申请号：US09330069

申请日：1999-06-11

Applicant: Eric J. Swanson

Inventor： Eric J. Swanson

IPC: H03M112

CPC classification number: H03M1/002 ,  G01K7/08

Abstract: Techniques are disclosed for permitting low power operation of a signal processing circuit, such as a mixed signal processing circuit, by operating devices of the digital signal processing side at an energy-delay minimum. To permit this to occur, the negative logic supply rail of the digital signal processing circuit is operated at a negative potential. This negative potential is generated using a charge pump on an integrated circuit chip which can be also used to create a negative substrate potential. A positive logic supply rail can be generated using a DC to DC converter or voltage regulator. The potential of the positive logic supply rail can be negative, as long at it is more positive than the potential of the negative logic supply rail.

Abstract translation: 公开了通过以能量延迟最小值操作数字信号处理侧的装置来允许诸如混合信号处理电路的信号处理电路的低功率操作的技术。 为了使其发生，数字信号处理电路的负逻辑电源轨工作在负电位。 该负电位是使用集成电路芯片上的电荷泵产生的，该集成电路芯片也可用于产生负的衬底电位。 可以使用DC-DC转换器或电压调节器产生正逻辑电源轨。 正逻辑供电轨的潜力可能是负的，只要它比负逻辑供电轨的潜力更积极。